User contributions
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- 15:50, 27 January 2021 (diff | hist) . . (+16) . . How to get best support from Verific
- 15:49, 27 January 2021 (diff | hist) . . (-30) . . How to get best support from Verific
- 22:16, 26 January 2021 (diff | hist) . . (+33) . . How to get best support from Verific
- 22:15, 26 January 2021 (diff | hist) . . (+1) . . How to get best support from Verific
- 22:14, 26 January 2021 (diff | hist) . . (+33) . . How to get best support from Verific
- 22:12, 26 January 2021 (diff | hist) . . (0) . . How to get best support from Verific
- 22:11, 26 January 2021 (diff | hist) . . (+39) . . How to get best support from Verific
- 22:10, 26 January 2021 (diff | hist) . . (+227) . . How to get best support from Verific
- 18:59, 26 January 2021 (diff | hist) . . (+138) . . How to get linefile data of macros - Macro callback function
- 18:05, 26 January 2021 (diff | hist) . . (+9,714) . . N How to get linefile data of macros - Macro callback function (Created page with "C++ application: <nowiki> #include <iostream> #include <sstream> #include "veri_file.h" #include "VeriTreeNode.h" #include "Map.h" using namespace std ; #ifdef VERIFIC_N...")
- 18:01, 26 January 2021 (diff | hist) . . (+148) . . Main Page
- 20:20, 7 January 2021 (diff | hist) . . (+10) . . Difference between RTL and gate-level simulations - Flipflop with async set and async reset
- 20:18, 7 January 2021 (diff | hist) . . (-2) . . Difference between RTL and gate-level simulations - Flipflop with async set and async reset
- 15:38, 7 January 2021 (diff | hist) . . (-1) . . Difference between RTL and gate-level simulations - Flipflop with async set and async reset
- 15:36, 7 January 2021 (diff | hist) . . (-3) . . Difference between RTL and gate-level simulations - Flipflop with async set and async reset
- 15:21, 7 January 2021 (diff | hist) . . (+6) . . Difference between RTL and gate-level simulations - Flipflop with async set and async reset
- 15:19, 7 January 2021 (diff | hist) . . (-2) . . Difference between RTL and gate-level simulations - Flipflop with async set and async reset
- 15:15, 7 January 2021 (diff | hist) . . (-98) . . Difference between RTL and gate-level simulations - Flipflop with async set and async reset
- 15:15, 7 January 2021 (diff | hist) . . (+5,337) . . N Difference between RTL and gate-level simulations - Flipflop with async set and async reset (Created page with "'''Difference between RTL and gate-level simulations - Flipflop with async set and async reset''' ''This article is inspired by an article by Clifford E. Cummings and Don Mil...")
- 15:04, 7 January 2021 (diff | hist) . . (+192) . . Main Page
- 13:34, 23 December 2020 (diff | hist) . . (-10) . . Verilog Port Expressions
- 13:33, 23 December 2020 (diff | hist) . . (+10) . . Verilog Port Expressions
- 11:26, 23 December 2020 (diff | hist) . . (+40) . . How Verific elaborator handles blackboxes/unknown boxes
- 10:45, 23 December 2020 (diff | hist) . . (+10) . . How Verific elaborator handles blackboxes/unknown boxes
- 10:00, 23 December 2020 (diff | hist) . . (+861) . . How Verific elaborator handles blackboxes/unknown boxes
- 23:52, 22 December 2020 (diff | hist) . . (-9) . . Black box, empty box, and unknown box
- 23:51, 22 December 2020 (diff | hist) . . (-14) . . How Verific elaborator handles blackboxes/unknown boxes
- 23:50, 22 December 2020 (diff | hist) . . (+14) . . How Verific elaborator handles blackboxes/unknown boxes
- 23:48, 22 December 2020 (diff | hist) . . (+142) . . Black box, empty box, and unknown box
- 23:46, 22 December 2020 (diff | hist) . . (+63) . . How Verific elaborator handles blackboxes/unknown boxes
- 18:45, 22 December 2020 (diff | hist) . . (+3,431) . . N How Verific elaborator handles blackboxes/unknown boxes (Created page with ">> This page is in progress << '''Q: After RTL elaboration on a Verilog design, I see Netlist with names such as 'NamedPorts' or 'OrderedPorts.' Sometimes in the Verilog netl...")
- 18:22, 22 December 2020 (diff | hist) . . (+129) . . Main Page
- 18:18, 22 December 2020 (diff | hist) . . (+10) . . Black box, empty box, and unknown box
- 17:32, 7 December 2020 (diff | hist) . . (+1,033) . . N Simple example of visitor pattern (Created page with " <nowiki> $ cat test.cpp #include <iostream> #include "veri_file.h" #include "VeriModule.h" #include "VeriVisitor.h" #include "VeriConstVal.h" #include "Strings.h" #ifdef V...")
- 17:29, 7 December 2020 (diff | hist) . . (+89) . . Main Page
- 13:49, 7 December 2020 (diff | hist) . . (+2,605) . . N Access attributes in parsetree (Created page with " <nowiki> #include "veri_file.h" #include "VeriModule.h" #include "VeriExpression.h" #include "VeriMisc.h" #include "VeriId.h" #include "Map.h" #include "Array.h" #include "...")
- 13:45, 7 December 2020 (diff | hist) . . (+90) . . Main Page
- 13:18, 7 December 2020 (diff | hist) . . (+242) . . Message handling
- 23:14, 17 November 2020 (diff | hist) . . (+224) . . How to get best support from Verific
- 16:09, 13 November 2020 (diff | hist) . . (+5) . . Main Page
- 16:07, 13 November 2020 (diff | hist) . . (+5,187) . . Type Range example with multi-dimensional arrays (current)
- 15:45, 7 October 2020 (diff | hist) . . (+22) . . LineFile data from input files
- 15:15, 1 October 2020 (diff | hist) . . (+2,137) . . N LineFile data from input files (Created page with "Verific uses the 'LineFile' manager to preserve line/file origination information from HDL source files. This info is annotated on all objects in parse trees and netlist datab...")
- 15:04, 1 October 2020 (diff | hist) . . (+70) . . Main Page
- 14:20, 15 September 2020 (diff | hist) . . (+8) . . How to get best support from Verific
- 12:05, 4 September 2020 (diff | hist) . . (+5) . . Simulation models for Verific primitives (current)
- 12:04, 4 September 2020 (diff | hist) . . (+98) . . N Simulation models for Verific primitives (Created page with "They are in example_designs/verilog/verificmodels.v and example_designs/verilog/verificsvamodels.v")
- 12:03, 4 September 2020 (diff | hist) . . (+143) . . Main Page
- 15:25, 24 August 2020 (diff | hist) . . (+5,984) . . N Fanout cone and grouping (Created page with "C++ code: <nowiki> →This application example collects instances in the fanout cone of a signal, and groups those instances into a new netlist: #include "Set.h" #include...")
- 15:20, 24 August 2020 (diff | hist) . . (+105) . . Main Page
- 10:39, 6 August 2020 (diff | hist) . . (+1,269) . . How to change name of id in Verilog parsetree
- 17:27, 30 July 2020 (diff | hist) . . (+800) . . Black box, empty box, and unknown box
- 17:06, 22 July 2020 (diff | hist) . . (+1,585) . . Included files associated with a Verilog source file (current)
- 16:44, 22 July 2020 (diff | hist) . . (+6) . . Included files associated with a Verilog source file
- 14:49, 20 July 2020 (diff | hist) . . (+2,448) . . N How to parse a string (Created page with "Let's say you want to add a node to the parsetree. One of the simple ways to do so is to start with a text string; then "parse" that string to get a VHDL or Verilog construct...")
- 14:29, 20 July 2020 (diff | hist) . . (+66) . . Main Page
- 14:10, 9 July 2020 (diff | hist) . . (+793) . . Access attributes of ports in parsetree (current)
- 13:01, 23 June 2020 (diff | hist) . . (+2,705) . . N How to create new module in Verilog parsetree (Created page with "This code sample also shows how to add new parameters and new ports to a module. C++: <nowiki> #include <iostream> #include "veri_file.h" #include "veri_tokens.h" #include...") (current)
- 12:58, 23 June 2020 (diff | hist) . . (+113) . . Main Page
- 12:31, 23 June 2020 (diff | hist) . . (+5,317) . . N How to get full hierarchy ID path (Created page with "Note that this code sample requires "Hierarchy Tree" feature. C++ code: <nowiki> #include "VerificSystem.h" #include "veri_file.h" #include "VeriModuleItem.h" #include "Veri...") (current)
- 12:30, 23 June 2020 (diff | hist) . . (-2) . . Main Page
- 12:24, 23 June 2020 (diff | hist) . . (+5,317) . . N Verilog/C++: How to get full hiererachy ID path : How to get full hiererachy ID path (Created page with "Note that this code sample requires "Hierarchy Tree" feature. C++ code: <nowiki> #include "VerificSystem.h" #include "veri_file.h" #include "VeriModuleItem.h" #include "Veri...") (current)
- 12:20, 23 June 2020 (diff | hist) . . (+91) . . Main Page
- 01:36, 15 June 2020 (diff | hist) . . (-300) . . System attributes
- 18:02, 5 June 2020 (diff | hist) . . (+3,126) . . Create a Netlist Database from scratch (not from RTL elaboration)
- 17:58, 5 June 2020 (diff | hist) . . (+4) . . Main Page
- 14:08, 5 June 2020 (diff | hist) . . (-128) . . Black box, empty box, and unknown box
- 17:44, 4 June 2020 (diff | hist) . . (+32) . . Black box, empty box, and unknown box
- 14:49, 4 June 2020 (diff | hist) . . (+11) . . Black box, empty box, and unknown box
- 14:43, 4 June 2020 (diff | hist) . . (+7,550) . . N Black box, empty box, and unknown box (Created page with "In Verific Netlist Database, a Netlist can be a black box, an empty box, or an unknown box. #An unknown box is a Netlist that is #*from an instantiation of an undefined Veril...")
- 14:07, 4 June 2020 (diff | hist) . . (+98) . . Main Page
- 17:47, 2 June 2020 (diff | hist) . . (+2,399) . . Message handling
- 17:29, 2 June 2020 (diff | hist) . . (+40) . . Main Page
- 14:12, 1 June 2020 (diff | hist) . . (+1,657) . . N Parsing from data in memory (Created page with "It is possible to use "stream input" to parse data in memory. The example below is For Verilog input, but it can be adapted to use for VHLD input as well. If you run this ap...") (current)
- 14:07, 1 June 2020 (diff | hist) . . (+82) . . Main Page
- 14:44, 14 May 2020 (diff | hist) . . (+49) . . How to use RegisterCallBackMsg() (current)
- 13:30, 14 May 2020 (diff | hist) . . (+3,157) . . N How to use RegisterCallBackMsg() (Created page with "Here is a small example showing how to use RegisterCallBackMsg(): <nowiki> #include <stdio.h> #include <stdarg.h> #include "Strings.h" #include "Map.h" // Make assoc...")
- 13:25, 14 May 2020 (diff | hist) . . (+84) . . Main Page
- 15:19, 13 May 2020 (diff | hist) . . (-10) . . Main Page
- 15:18, 13 May 2020 (diff | hist) . . (+10) . . Main Page
- 20:05, 8 May 2020 (diff | hist) . . (+1) . . System attributes
- 20:03, 8 May 2020 (diff | hist) . . (+12) . . System attributes
- 13:40, 6 May 2020 (diff | hist) . . (+2) . . What VeriModule* or VhdlPrimaryUnit* the Netlist comes from? (current)
- 13:40, 6 May 2020 (diff | hist) . . (+19) . . What VeriModule* or VhdlPrimaryUnit* the Netlist comes from?
- 13:03, 6 May 2020 (diff | hist) . . (+1) . . Macro Callback example (current)
- 13:12, 28 April 2020 (diff | hist) . . (-2) . . How to get best support from Verific
- 13:11, 28 April 2020 (diff | hist) . . (+318) . . How to get best support from Verific
- 11:09, 28 April 2020 (diff | hist) . . (-4) . . How to get best support from Verific
- 12:06, 26 March 2020 (diff | hist) . . (+39) . . Does Verific support XMR?
- 19:03, 14 February 2020 (diff | hist) . . (+30) . . System attributes
- 12:36, 14 February 2020 (diff | hist) . . (-4) . . System attributes
- 12:35, 14 February 2020 (diff | hist) . . (+2) . . System attributes
- 12:33, 14 February 2020 (diff | hist) . . (+323) . . System attributes
- 12:08, 14 February 2020 (diff | hist) . . (+4) . . System attributes
- 12:07, 14 February 2020 (diff | hist) . . (+2) . . System attributes
- 15:20, 13 February 2020 (diff | hist) . . (+46) . . System attributes
- 14:42, 13 February 2020 (diff | hist) . . (-1) . . System attributes
- 14:42, 13 February 2020 (diff | hist) . . (-40) . . System attributes
- 14:41, 13 February 2020 (diff | hist) . . (+2,540) . . N System attributes (Created page with "Verific system attributes are attributes added and attached to DesignObjs (Design Objects) during the process of building the Netlist Database. To distinguish with user-decla...")
- 14:27, 13 February 2020 (diff | hist) . . (+62) . . Main Page
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