User contributions
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- 12:35, 14 February 2020 (diff | hist) . . (+2) . . System attributes
- 12:33, 14 February 2020 (diff | hist) . . (+323) . . System attributes
- 12:08, 14 February 2020 (diff | hist) . . (+4) . . System attributes
- 12:07, 14 February 2020 (diff | hist) . . (+2) . . System attributes
- 15:20, 13 February 2020 (diff | hist) . . (+46) . . System attributes
- 14:42, 13 February 2020 (diff | hist) . . (-1) . . System attributes
- 14:42, 13 February 2020 (diff | hist) . . (-40) . . System attributes
- 14:41, 13 February 2020 (diff | hist) . . (+2,540) . . N System attributes (Created page with "Verific system attributes are attributes added and attached to DesignObjs (Design Objects) during the process of building the Netlist Database. To distinguish with user-decla...")
- 14:27, 13 February 2020 (diff | hist) . . (+62) . . Main Page
- 17:04, 12 February 2020 (diff | hist) . . (+2,764) . . N Using stream input to ignore input file (Created page with "This example shows how to use stream input to ignore input files that meet certain conditions. The example uses only filename as the "ignore" category. But you can have other...") (current)
- 16:59, 12 February 2020 (diff | hist) . . (+101) . . Main Page
- 16:02, 10 February 2020 (diff | hist) . . (+9,156) . . N Bit-blasting a multi-port RAM instance (Created page with "'''Q: What is bit-blasting a multi-port RAM instance''' Verific’s RAM extraction creates a minimal-port, multi-port RAM model in the netlist for every identifier that behav...") (current)
- 15:55, 10 February 2020 (diff | hist) . . (+103) . . Main Page
- 18:30, 3 February 2020 (diff | hist) . . (+8) . . Main Page
- 17:53, 31 January 2020 (diff | hist) . . (+4,658) . . Memory elements of a RamNet (current)
- 14:00, 29 January 2020 (diff | hist) . . (+21) . . How to check for errors in analysis/elaboration (current)
- 13:13, 29 January 2020 (diff | hist) . . (0) . . How to check for errors in analysis/elaboration
- 13:12, 29 January 2020 (diff | hist) . . (+69) . . How to check for errors in analysis/elaboration
- 13:07, 29 January 2020 (diff | hist) . . (+257) . . How to check for errors in analysis/elaboration
- 18:27, 22 January 2020 (diff | hist) . . (+1) . . Main Page
- 18:25, 22 January 2020 (diff | hist) . . (+4,836) . . N Type Range example with multi-dimensional arrays (Created page with "For a design with multidimensional arrays, the application needs to create a data structure for mapping NetBus to TypeRange. C++: <nowiki> #include <iostream> #include "veri...")
- 18:21, 22 January 2020 (diff | hist) . . (+127) . . Main Page
- 18:06, 22 January 2020 (diff | hist) . . (+3,406) . . N Memory elements of a RamNet (Created page with "In Verific Netlist Database, a RamNet is created for every identifier in the parsetree that is inferred as multi-port memory. This example checks what memory elements are con...")
- 18:02, 22 January 2020 (diff | hist) . . (+78) . . Main Page
- 17:04, 22 January 2020 (diff | hist) . . (+17) . . Main Page
- 17:53, 21 January 2020 (diff | hist) . . (+1) . . How to tell if a module has encrypted contents
- 17:53, 21 January 2020 (diff | hist) . . (+6,736) . . N How to tell if a module has encrypted contents (Created page with "C++ <nowiki> #include <cstring> // for memset #include "veri_file.h" // Make verilog reader available #include "VeriModule.h" // Definition of a VeriModule...")
- 17:50, 21 January 2020 (diff | hist) . . (+115) . . Main Page
- 17:30, 21 January 2020 (diff | hist) . . (+6) . . How to get best support from Verific
- 16:02, 21 January 2020 (diff | hist) . . (0) . . Visiting Hierarchical References (VeriSelectedName)
- 16:02, 21 January 2020 (diff | hist) . . (+6) . . Visiting Hierarchical References (VeriSelectedName)
- 15:59, 21 January 2020 (diff | hist) . . (+3,014) . . N Visiting Hierarchical References (VeriSelectedName) (Created page with "In Verilog parsetree, hierarchical references are of type VeriSelectedName. Note that the "_suffix_id" fields are resolved only in statically-elaborated parsetree. In other wo...")
- 15:54, 21 January 2020 (diff | hist) . . (+2) . . Main Page
- 15:52, 21 January 2020 (diff | hist) . . (+124) . . Main Page
- 17:58, 22 October 2019 (diff | hist) . . (0) . . How to get all Verilog files being analyzed
- 14:55, 4 October 2019 (diff | hist) . . (+2,118) . . N How to ignore a (not used) parameter/generic in elaboration. (Created page with "'''Q: How do I specify the elaborator to ignore parameter/generic that is not used?''' In RTL or static elaboration, parameterized instances are uniquified. For example, this...") (current)
- 14:37, 4 October 2019 (diff | hist) . . (+144) . . Main Page
- 14:11, 21 August 2019 (diff | hist) . . (+2,642) . . N Getting instances' parameters (Created page with "C++: <nowiki> #include "Map.h" #include "Array.h" #include "veri_file.h" #include "VeriModule.h" #include "VeriExpression.h" #include "VeriId.h" #include "VeriScope.h" #ifd...") (current)
- 14:07, 21 August 2019 (diff | hist) . . (+81) . . Main Page
- 12:21, 14 August 2019 (diff | hist) . . (-27) . . Comment out a line using test-based design modification and parsetree modification (current)
- 13:02, 30 July 2019 (diff | hist) . . (+629) . . Prettyprint all modules in the design hierarchy
- 17:10, 29 July 2019 (diff | hist) . . (-23) . . Prettyprint all modules in the design hierarchy
- 17:08, 29 July 2019 (diff | hist) . . (-1,484) . . Prettyprint all modules in the design hierarchy
- 23:29, 28 July 2019 (diff | hist) . . (-1) . . Prettyprint all modules in the design hierarchy
- 23:28, 28 July 2019 (diff | hist) . . (0) . . Prettyprint all modules in the design hierarchy
- 23:26, 28 July 2019 (diff | hist) . . (-2) . . Prettyprint all modules in the design hierarchy
- 23:25, 28 July 2019 (diff | hist) . . (-14) . . Prettyprint all modules in the design hierarchy
- 23:24, 28 July 2019 (diff | hist) . . (+12) . . Prettyprint all modules in the design hierarchy
- 23:22, 28 July 2019 (diff | hist) . . (+7,879) . . N Prettyprint all modules in the design hierarchy (Created page with "There is an API to prettyprint a module, and there is an API to prettyprint all modules in a library. But there is no single API to prettyprint all modules in the design hier...")
- 23:16, 28 July 2019 (diff | hist) . . (+117) . . Main Page
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