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- 14:14, 28 August 2024 (diff | hist) . . (-1) . . Create DOT diagram of parse tree (current)
- 14:12, 28 August 2024 (diff | hist) . . (+615) . . Create DOT diagram of parse tree
- 09:05, 23 August 2024 (diff | hist) . . (+6) . . Yosys-Verific Integration (current)
- 21:24, 16 August 2024 (diff | hist) . . (+1,219) . . N Yosys-Verific Integration (Created page with "Yosys is an open source platform that works with a suite of EDA tools. It is possible for a Verific user to integrate Verific with Yosys, which would replace the open source...")
- 21:18, 16 August 2024 (diff | hist) . . (+60) . . Main Page
- 21:44, 22 July 2024 (diff | hist) . . (+7) . . Traverse instances in parsetree (current)
- 21:40, 22 July 2024 (diff | hist) . . (+3,601) . . Traverse instances in parsetree
- 19:08, 12 January 2024 (diff | hist) . . (+4) . . Create DOT diagram of parse tree
- 19:05, 12 January 2024 (diff | hist) . . (+24) . . Create DOT diagram of parse tree
- 18:59, 12 January 2024 (diff | hist) . . (+2) . . Main Page
- 18:57, 12 January 2024 (diff | hist) . . (+4,191) . . N Create DOT diagram of parse tree (Created page with "This example parses the r4000 design in the <verific>/example_designs/verilog directory and writes out a Graphviz DOT-format file that represents a simple diagram view of th...")
- 18:38, 12 January 2024 (diff | hist) . . (+87) . . Main Page
- 08:37, 23 October 2023 (diff | hist) . . (+14) . . Modules/design units with " default" suffix in their names
- 08:36, 23 October 2023 (diff | hist) . . (+11) . . Main Page
- 08:29, 23 October 2023 (diff | hist) . . (+1,584) . . Modules/design units with " default" suffix in their names
- 11:04, 19 April 2023 (diff | hist) . . (+41) . . Instance - Module binding order
- 20:31, 2 March 2023 (diff | hist) . . (+99) . . Compile-time/run-time flags (current)
- 20:19, 2 March 2023 (diff | hist) . . (-10) . . Compile-time/run-time flags
- 20:11, 2 March 2023 (diff | hist) . . (-1) . . Compile-time/run-time flags
- 20:05, 2 March 2023 (diff | hist) . . (+2,319) . . Compile-time/run-time flags
- 11:14, 17 February 2023 (diff | hist) . . (0) . . How to ignore parameters/generics in elaboration (current)
- 17:08, 22 September 2022 (diff | hist) . . (0) . . Pretty-print a module and the packages imported by the module
- 11:28, 13 September 2022 (diff | hist) . . (-30) . . Python pretty-printer for gdb (current)
- 11:10, 13 September 2022 (diff | hist) . . (+30) . . Python pretty-printer for gdb
- 11:06, 13 September 2022 (diff | hist) . . (+5,262) . . N Python pretty-printer for gdb (Created page with "If gdb (GNU debugger) was compiled with Python support, it is possible to run Python scripts within gdb. Below is an example of how to create a custom pretty-printer for Veri...")
- 10:46, 13 September 2022 (diff | hist) . . (+68) . . Main Page
- 17:46, 11 May 2022 (diff | hist) . . (+68) . . m How to get packed dimensions of enum (current)
- 11:44, 2 May 2022 (diff | hist) . . (+5) . . Parse select modules only and ignore the rest
- 11:44, 2 May 2022 (diff | hist) . . (+35) . . Parse select modules only and ignore the rest
- 11:39, 2 May 2022 (diff | hist) . . (+145) . . Parse select modules only and ignore the rest
- 11:33, 2 May 2022 (diff | hist) . . (+2,799) . . N Parse select modules only and ignore the rest (Created page with "There is no API to parse only a subset of modules of a design that contains many modules. However, this can be accomplished through Verific's processing of v-files. Below i...")
- 11:00, 2 May 2022 (diff | hist) . . (+113) . . Main Page
- 11:26, 1 April 2022 (diff | hist) . . (+44) . . Main Page
- 11:25, 1 April 2022 (diff | hist) . . (+5) . . Main Page
- 11:24, 1 April 2022 (diff | hist) . . (0) . . Preserving nets (Redirected page to Preserving user nets - preventing nets from being optimized away) (current)
- 11:20, 1 April 2022 (diff | hist) . . (-5) . . Main Page
- 11:20, 1 April 2022 (diff | hist) . . (+5) . . Main Page
- 11:17, 1 April 2022 (diff | hist) . . (+4) . . Preserving user nets - preventing nets from being optimized away (current)
- 11:16, 1 April 2022 (diff | hist) . . (+78) . . N Preserving user nets --preventing nets from being optimized away (Vince moved page Preserving user nets --preventing nets from being optimized away to Preserving user nets - preventing nets from being optimized away) (current)
- 11:16, 1 April 2022 (diff | hist) . . (0) . . m Preserving user nets - preventing nets from being optimized away (Vince moved page Preserving user nets --preventing nets from being optimized away to Preserving user nets - preventing nets from being optimized away)
- 11:16, 1 April 2022 (diff | hist) . . (+4) . . Main Page
- 11:13, 1 April 2022 (diff | hist) . . (+78) . . N Preserving nets (Vince moved page Preserving nets to Preserving user nets --preventing nets from being optimized away: rename for clarify)
- 11:13, 1 April 2022 (diff | hist) . . (0) . . m Preserving user nets - preventing nets from being optimized away (Vince moved page Preserving nets to Preserving user nets --preventing nets from being optimized away: rename for clarify)
- 11:12, 1 April 2022 (diff | hist) . . (-53) . . Main Page (Undo revision 764 by Vince (talk))
- 11:10, 1 April 2022 (diff | hist) . . (+53) . . Main Page
- 11:07, 1 April 2022 (diff | hist) . . (+2,211) . . N Preserving user nets - preventing nets from being optimized away (Created page with "'''Q: How do I preserve user-declared nets so that they don't get optimized away? I would like to see them written out to the netlist file.''' There are two approaches : * gl...")
- 10:38, 1 April 2022 (diff | hist) . . (+85) . . Main Page
- 08:44, 11 February 2022 (diff | hist) . . (+122) . . How to save computer resources
- 10:51, 3 November 2021 (diff | hist) . . (+571) . . Black box, empty box, and unknown box
- 08:57, 20 October 2021 (diff | hist) . . (+1) . . m How to get all Verilog files being analyzed (current)
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