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- 14:29, 27 July 2016 (diff | hist) . . (+94) . . m Main Page
- 14:34, 26 July 2016 (diff | hist) . . (+1,053) . . N Included files associated with a Verilog source file (Created page with "'''Q: How do I get the list of included files associated with a Verilog source file?''' The main utility you require is: static Map *veri_file::GetIncludedFiles() ; It re...")
- 14:31, 26 July 2016 (diff | hist) . . (+140) . . m Main Page
- 14:01, 26 July 2016 (diff | hist) . . (+617) . . N Remove Verific data structures (Created page with "'''Q: How do I remove all Verific data structures in memory?''' To remove Verilog parsetree: veri_file::ResetParser(); To remove VHDL parsetree: vhdl_file::ResetPa...")
- 13:51, 26 July 2016 (diff | hist) . . (+94) . . m Main Page
- 13:15, 25 July 2016 (diff | hist) . . (+23) . . m How to get all Verilog files being analyzed
- 13:11, 25 July 2016 (diff | hist) . . (+107) . . m How to get all Verilog files being analyzed
- 18:10, 22 July 2016 (diff | hist) . . (+7) . . m Main Page
- 17:36, 22 July 2016 (diff | hist) . . (+10) . . m Main Page
- 17:34, 22 July 2016 (diff | hist) . . (+327) . . N Output file formats (Created page with "'''Q: What language formats does Verific software support as output?''' Verific software can write out: * RTL Verilog/SystemVerilog (from parsetree) * RTL VHDL (from parsetr...") (current)
- 17:30, 22 July 2016 (diff | hist) . . (0) . . m Main Page
- 17:30, 22 July 2016 (diff | hist) . . (-2) . . m Main Page
- 17:29, 22 July 2016 (diff | hist) . . (+64) . . m Main Page
- 16:54, 22 July 2016 (diff | hist) . . (+38) . . m Design with System Verilog and Verilog 2001 files
- 16:12, 22 July 2016 (diff | hist) . . (+17) . . m Does Verific support XMR?
- 16:10, 22 July 2016 (diff | hist) . . (+32) . . m Verific data structures
- 16:03, 22 July 2016 (diff | hist) . . (+24) . . m Does Verific build CDFG?
- 16:02, 22 July 2016 (diff | hist) . . (+275) . . N What languages can I use with Verific software? (Created page with "'''Q: What programming languages can I use with Verific software?''' Verific software is written in C++. But with [http://www.swig.org/ SWIG], all APIs are ported to Tcl, Pe...")
- 15:57, 22 July 2016 (diff | hist) . . (+118) . . m Main Page
- 15:56, 22 July 2016 (diff | hist) . . (-117) . . Main Page (Undo revision 211 by Hoa (talk))
- 15:54, 22 July 2016 (diff | hist) . . (+117) . . m Main Page
- 15:43, 22 July 2016 (diff | hist) . . (+8) . . m Main Page
- 15:43, 22 July 2016 (diff | hist) . . (0) . . m Verific data structures
- 15:03, 22 July 2016 (diff | hist) . . (+847) . . N How to get all Verilog files being analyzed (Created page with "'''Q: I'm using -v, -y, .... After Verific is done with the analysis, how do I get a list of all the files being analyzed?''' Use this code: Array analyzed_files ; // Array...")
- 15:03, 22 July 2016 (diff | hist) . . (+26) . . m Main Page
- 15:01, 22 July 2016 (diff | hist) . . (+672) . . N What VeriModule* or VhdlPrimaryUnit* the Netlist comes from? (Created page with "'''Q: While looking at a Netlist, is there a clean way to look back at what VeriModule* or VhdlPrimaryUnit* this netlist was derived from? ''' For example, a module: mod...")
- 15:01, 22 July 2016 (diff | hist) . . (+34) . . m Main Page
- 14:58, 22 July 2016 (diff | hist) . . (+1,602) . . N Verilog Port Expressions (Created page with "'''Q: Why are the ports in original Verilog file renamed to p1, p2, ....?''' Input file: module foo ( datain[0], datain[0] →same net into multiple port expression: ,...")
- 14:58, 22 July 2016 (diff | hist) . . (+8) . . m Main Page
- 14:57, 22 July 2016 (diff | hist) . . (-1) . . m Design with System Verilog and Verilog 2001 files
- 14:56, 22 July 2016 (diff | hist) . . (+875) . . N Design with System Verilog and Verilog 2001 files (Created page with "'''Q: For a design consisting of a mixture of Verilog 2001 and SystemVerilog input files, should I parse all the files as SystemVerilog?''' The set of SystemVerilog construc...")
- 14:56, 22 July 2016 (diff | hist) . . (+17) . . m Main Page
- 14:51, 22 July 2016 (diff | hist) . . (-84) . . m Design with VHDL-1993 and VHDL-2008 files
- 14:51, 22 July 2016 (diff | hist) . . (+739) . . N Design with VHDL-1993 and VHDL-2008 files (Created page with "'''Q: A customer wants to analyze/elaborate different VHDL flavors (1993 and 2008). They want to process the 93 files first and then the 08. As each flavor has its own IEEE li...")
- 14:50, 22 July 2016 (diff | hist) . . (-80) . . m Main Page
- 14:46, 22 July 2016 (diff | hist) . . (+9) . . m How to get module ports from Verilog parsetree (current)
- 14:45, 22 July 2016 (diff | hist) . . (+240) . . N Original RTL language (Created page with "'''Q: How do I know what language a Netlist in the netlist database comes from?''' Use attribute " language" (note the leading space): Netlist *nl; nl->GetAttValue("...")
- 14:44, 22 July 2016 (diff | hist) . . (+8) . . m Main Page
- 14:42, 22 July 2016 (diff | hist) . . (0) . . m Does Verific build CDFG?
- 14:41, 22 July 2016 (diff | hist) . . (+6) . . Does Verific build CDFG?
- 14:41, 22 July 2016 (diff | hist) . . (+65) . . m Does Verific build CDFG?
- 14:39, 22 July 2016 (diff | hist) . . (+852) . . N Does Verific support XMR? (Created page with "'''Q: Does Verific support cross module references (XMR)?''' Verific fully supports XMR with "hierarchy tree" feature. Please refer to http://www.verific.com/docs/index.php?t...")
- 14:39, 22 July 2016 (diff | hist) . . (-1) . . Main Page
- 14:37, 22 July 2016 (diff | hist) . . (+1,891) . . N Verific data structures (Created page with "'''Q: What are the data structures in Verific?''' There are 2 data structures in Verific: parsetree and netlist database. 1. The parsetree is just another representation of...")
- 14:36, 22 July 2016 (diff | hist) . . (+6) . . m Main Page
- 14:35, 22 July 2016 (diff | hist) . . (+1,891) . . N Verific data structure (Created page with "'''Q: What are the data structures in Verific?''' There are 2 data structures in Verific: parsetree and netlist database. 1. The parsetree is just another representation of...") (current)
- 13:29, 22 July 2016 (diff | hist) . . (-6) . . Main Page (Undo revision 184 by Hoa (talk))
- 13:27, 22 July 2016 (diff | hist) . . (+6) . . Main Page
- 13:26, 22 July 2016 (diff | hist) . . (+166) . . m How to get module ports from Verilog parsetree
- 13:21, 22 July 2016 (diff | hist) . . (+8) . . m How to get module ports from Verilog parsetree
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