User contributions
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- 16:29, 22 November 2016 (diff | hist) . . (+910) . . m How to get all Verilog files being analyzed
- 15:55, 26 October 2016 (diff | hist) . . (+1,842) . . N How to get type/initial value of parameters (Created page with "'''Q: Why do I get type and initial value of parameters?''' Example Perl code: #!/usr/bin/perl # push(@INC,"../../../perlmain/install"); require "Verific.pm"; #...")
- 15:49, 26 October 2016 (diff | hist) . . (+106) . . Main Page
- 15:43, 26 October 2016 (diff | hist) . . (+90) . . Main Page
- 15:43, 26 October 2016 (diff | hist) . . (+430) . . N Prettyprint to a string (Created page with "'''Q: Why do I prettyprint a Verilog parsetree node to a string?''' Example code: VeriExpression *init_value = param_id -> GetInitialValue(); if (init_value)...")
- 11:49, 22 September 2016 (diff | hist) . . (+413) . . m Does Verific support XMR?
- 16:15, 4 August 2016 (diff | hist) . . (+5) . . m Main Page
- 16:14, 4 August 2016 (diff | hist) . . (+602) . . N Message handling (Created page with "'''Q: How do I upgrade/downgrade messages from Verific?''' For C++, use the following APIs: Message::SetMessageType() - Force a message type by message id Message::Ge...")
- 16:08, 4 August 2016 (diff | hist) . . (+71) . . m Main Page
- 16:33, 1 August 2016 (diff | hist) . . (+1) . . Constant expression replacement
- 16:32, 1 August 2016 (diff | hist) . . (+495) . . N Constant expression replacement (Created page with "'''Q: Does Verific replace constant expressions with their respective values?''' I have in my Verilog code: parameter size = 8; reg [size-1:0] foo; I expect the range...")
- 16:28, 1 August 2016 (diff | hist) . . (+121) . . m Main Page
- 11:43, 28 July 2016 (diff | hist) . . (-12) . . Remove Verific data structures
- 11:42, 28 July 2016 (diff | hist) . . (-32) . . m Remove Verific data structures
- 11:41, 28 July 2016 (diff | hist) . . (+24) . . m Remove Verific data structures
- 16:13, 27 July 2016 (diff | hist) . . (+11) . . m Main Page
- 16:12, 27 July 2016 (diff | hist) . . (+879) . . N SystemVerilog "std" package (Created page with "'''Q: Support for SystemVerilog semaphore/process/mailbox.''' When I analyzed my SystemVerilog file, Verific issued error message: test.sv(4): ERROR: process is not declare...")
- 16:05, 27 July 2016 (diff | hist) . . (+1) . . m Main Page
- 16:04, 27 July 2016 (diff | hist) . . (+97) . . m Main Page
- 16:02, 27 July 2016 (diff | hist) . . (+21) . . m Main Page
- 16:02, 27 July 2016 (diff | hist) . . (0) . . m Main Page
- 16:00, 27 July 2016 (diff | hist) . . (+65) . . m Main Page
- 15:46, 27 July 2016 (diff | hist) . . (-2) . . m Compile-time/run-time flags
- 15:40, 27 July 2016 (diff | hist) . . (+3) . . Compile-time/run-time flags
- 15:39, 27 July 2016 (diff | hist) . . (+790) . . N Compile-time/run-time flags (Created page with "'''Q: Are there options to control Verific software's behavior?''' There are compile-time flags and run-time flags to control Verific software's behavior. The compile-time f...")
- 15:29, 27 July 2016 (diff | hist) . . (+94) . . m Main Page
- 15:34, 26 July 2016 (diff | hist) . . (+1,053) . . N Included files associated with a Verilog source file (Created page with "'''Q: How do I get the list of included files associated with a Verilog source file?''' The main utility you require is: static Map *veri_file::GetIncludedFiles() ; It re...")
- 15:31, 26 July 2016 (diff | hist) . . (+140) . . m Main Page
- 15:01, 26 July 2016 (diff | hist) . . (+617) . . N Remove Verific data structures (Created page with "'''Q: How do I remove all Verific data structures in memory?''' To remove Verilog parsetree: veri_file::ResetParser(); To remove VHDL parsetree: vhdl_file::ResetPa...")
- 14:51, 26 July 2016 (diff | hist) . . (+94) . . m Main Page
- 14:15, 25 July 2016 (diff | hist) . . (+23) . . m How to get all Verilog files being analyzed
- 14:11, 25 July 2016 (diff | hist) . . (+107) . . m How to get all Verilog files being analyzed
- 19:10, 22 July 2016 (diff | hist) . . (+7) . . m Main Page
- 18:36, 22 July 2016 (diff | hist) . . (+10) . . m Main Page
- 18:34, 22 July 2016 (diff | hist) . . (+327) . . N Output file formats (Created page with "'''Q: What language formats does Verific software support as output?''' Verific software can write out: * RTL Verilog/SystemVerilog (from parsetree) * RTL VHDL (from parsetr...") (current)
- 18:30, 22 July 2016 (diff | hist) . . (0) . . m Main Page
- 18:30, 22 July 2016 (diff | hist) . . (-2) . . m Main Page
- 18:29, 22 July 2016 (diff | hist) . . (+64) . . m Main Page
- 17:54, 22 July 2016 (diff | hist) . . (+38) . . m Design with System Verilog and Verilog 2001 files
- 17:12, 22 July 2016 (diff | hist) . . (+17) . . m Does Verific support XMR?
- 17:10, 22 July 2016 (diff | hist) . . (+32) . . m Verific data structures
- 17:03, 22 July 2016 (diff | hist) . . (+24) . . m Does Verific build CDFG?
- 17:02, 22 July 2016 (diff | hist) . . (+275) . . N What languages can I use with Verific software? (Created page with "'''Q: What programming languages can I use with Verific software?''' Verific software is written in C++. But with [http://www.swig.org/ SWIG], all APIs are ported to Tcl, Pe...")
- 16:57, 22 July 2016 (diff | hist) . . (+118) . . m Main Page
- 16:56, 22 July 2016 (diff | hist) . . (-117) . . Main Page (Undo revision 211 by Hoa (talk))
- 16:54, 22 July 2016 (diff | hist) . . (+117) . . m Main Page
- 16:43, 22 July 2016 (diff | hist) . . (+8) . . m Main Page
- 16:43, 22 July 2016 (diff | hist) . . (0) . . m Verific data structures
- 16:03, 22 July 2016 (diff | hist) . . (+847) . . N How to get all Verilog files being analyzed (Created page with "'''Q: I'm using -v, -y, .... After Verific is done with the analysis, how do I get a list of all the files being analyzed?''' Use this code: Array analyzed_files ; // Array...")
- 16:03, 22 July 2016 (diff | hist) . . (+26) . . m Main Page
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