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- 15:51, 22 July 2016 (diff | hist) . . (+739) . . N Design with VHDL-1993 and VHDL-2008 files (Created page with "'''Q: A customer wants to analyze/elaborate different VHDL flavors (1993 and 2008). They want to process the 93 files first and then the 08. As each flavor has its own IEEE li...")
- 15:50, 22 July 2016 (diff | hist) . . (-80) . . m Main Page
- 15:46, 22 July 2016 (diff | hist) . . (+9) . . m How to get module ports from Verilog parsetree (current)
- 15:45, 22 July 2016 (diff | hist) . . (+240) . . N Original RTL language (Created page with "'''Q: How do I know what language a Netlist in the netlist database comes from?''' Use attribute " language" (note the leading space): Netlist *nl; nl->GetAttValue("...")
- 15:44, 22 July 2016 (diff | hist) . . (+8) . . m Main Page
- 15:42, 22 July 2016 (diff | hist) . . (0) . . m Does Verific build CDFG?
- 15:41, 22 July 2016 (diff | hist) . . (+6) . . Does Verific build CDFG?
- 15:41, 22 July 2016 (diff | hist) . . (+65) . . m Does Verific build CDFG?
- 15:39, 22 July 2016 (diff | hist) . . (+852) . . N Does Verific support XMR? (Created page with "'''Q: Does Verific support cross module references (XMR)?''' Verific fully supports XMR with "hierarchy tree" feature. Please refer to http://www.verific.com/docs/index.php?t...")
- 15:39, 22 July 2016 (diff | hist) . . (-1) . . Main Page
- 15:37, 22 July 2016 (diff | hist) . . (+1,891) . . N Verific data structures (Created page with "'''Q: What are the data structures in Verific?''' There are 2 data structures in Verific: parsetree and netlist database. 1. The parsetree is just another representation of...")
- 15:36, 22 July 2016 (diff | hist) . . (+6) . . m Main Page
- 15:35, 22 July 2016 (diff | hist) . . (+1,891) . . N Verific data structure (Created page with "'''Q: What are the data structures in Verific?''' There are 2 data structures in Verific: parsetree and netlist database. 1. The parsetree is just another representation of...") (current)
- 14:29, 22 July 2016 (diff | hist) . . (-6) . . Main Page (Undo revision 184 by Hoa (talk))
- 14:27, 22 July 2016 (diff | hist) . . (+6) . . Main Page
- 14:26, 22 July 2016 (diff | hist) . . (+166) . . m How to get module ports from Verilog parsetree
- 14:21, 22 July 2016 (diff | hist) . . (+8) . . m How to get module ports from Verilog parsetree
- 13:07, 22 July 2016 (diff | hist) . . (+380) . . N How to get module ports from Verilog parsetree (Created page with "From the Verilog parsetree, how can I get the ports of a module? You can use the following APIs: VeriModule::GetPorts() to get the ports (Array of VeriIdDef *) from a module...")
- 13:04, 22 July 2016 (diff | hist) . . (+119) . . Main Page
- 13:01, 22 July 2016 (diff | hist) . . (+1) . . m Main Page (Undo revision 178 by Hoa (talk))
- 13:00, 22 July 2016 (diff | hist) . . (-1) . . m Main Page
- 12:58, 22 July 2016 (diff | hist) . . (+18) . . m Does Verific build CDFG?
- 12:58, 22 July 2016 (diff | hist) . . (+85) . . N Does Verific build CDFG? (Created page with "No, it does not. See [http://www.verific.com/faq/index.php?title=What_are_the_data].")
- 12:57, 22 July 2016 (diff | hist) . . (+88) . . m Main Page
- 12:55, 22 July 2016 (diff | hist) . . (+298) . . m What are the data (current)
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