Main Page

General

• How do I know what language a Netlist in the netlist database comes from?
• What are the data structures in Verific?
• How do I remove all Verific data structures in memory?
• Does Verific build control and data flow graph (CDFG)?
• Does Verific support cross module references (XMR)?
• Are there options to control Verific software's behavior?

VHDL, Verilog, Liberty, EDIF

• Verilog: I'm using -v, -y, .... After Verific is done with the analysis, how do I get a list of all the files being analyzed?
• Verilog: How do I get the list of included files associated with a Verilog source file?
• Verilog: Why are the ports in original Verilog file renamed to p1, p2, ....?
• Verilog: For a design consisting of a mixture of Verilog 2001 and SystemVerilog input files, should I parse all the files as SystemVerilog?
• Verilog: From the Verilog parsetree, how can I get the ports of a module?
• VHDL: VHDL-1993 and VHDL-2008 each has its own IEEE library set. How do I analyze/elaborate a design with a mixture of files of different VHDL dialects (1993 and 2008)?
• Verilog/VHDL: While looking at a Netlist, is there a clean way to look back at what VeriModule* or VhdlPrimaryUnit* this netlist was derived from?

Output

• What language formats does Verific support as output?

TCL, Perl, Python, Java

• What programming languages can I use with Verific software?