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- 13:49, 8 August 2023 (diff | hist) . . (-2) . . Static elaboration
- 13:49, 8 August 2023 (diff | hist) . . (+43) . . Static elaboration
- 13:48, 8 August 2023 (diff | hist) . . (+31) . . Static elaboration
- 11:34, 2 August 2023 (diff | hist) . . (+1,679) . . N How to use RegisterPragmaRefCallBack() (Created page with "Here is a small example showing how to use RegisterPragmaRefCallBack(): <nowiki> #include <iostream> #include "veri_file.h" #include "vhdl_file.h" #include "Message.h" usin...") (current)
- 11:25, 2 August 2023 (diff | hist) . . (+96) . . Main Page
- 07:40, 26 July 2023 (diff | hist) . . (+57) . . How to get linefile data of macros - Macro callback function
- 07:51, 16 June 2023 (diff | hist) . . (+90) . . Escaped identifiers in RTL files and in Verific data structures (current)
- 16:23, 5 June 2023 (diff | hist) . . (+1,333) . . Parse select modules only and ignore the rest (current)
- 12:58, 24 April 2023 (diff | hist) . . (+3,728) . . N In Verilog parsetree adding names to unnamed instances (Created page with "In Verilog, each module instantiation should have a name. But name is optional for UDP instantiation and Verilog primitive instantiation. Verific issues a warning for unnamed...")
- 12:50, 24 April 2023 (diff | hist) . . (+1) . . Main Page
- 12:50, 24 April 2023 (diff | hist) . . (+130) . . Main Page
- 14:02, 14 March 2023 (diff | hist) . . (-2) . . Difference between RTL and gate-level simulations - Flipflop with async set and async reset (current)
- 13:59, 14 March 2023 (diff | hist) . . (0) . . Difference between RTL and gate-level simulations - Flipflop with async set and async reset
- 10:23, 24 February 2023 (diff | hist) . . (-34) . . Notes on analysis
- 10:26, 21 February 2023 (diff | hist) . . (+26) . . Instance - Module binding order
- 13:40, 13 February 2023 (diff | hist) . . (+3,195) . . Verilog Port Expressions (current)
- 09:59, 10 February 2023 (diff | hist) . . (+1,742) . . Verilog Port Expressions
- 09:30, 10 February 2023 (diff | hist) . . (-51) . . Main Page
- 09:27, 10 February 2023 (diff | hist) . . (0) . . m Verilog Port Expressions (Hoa moved page Verilog ports being renamed to Verilog Port Expressions)
- 09:27, 10 February 2023 (diff | hist) . . (+38) . . N Verilog ports being renamed (Hoa moved page Verilog ports being renamed to Verilog Port Expressions) (current)
- 14:59, 25 January 2023 (diff | hist) . . (+296) . . How to get best support from Verific
- 09:35, 15 December 2022 (diff | hist) . . (+116) . . Static elaboration
- 14:32, 17 November 2022 (diff | hist) . . (+6,695) . . N Evaluate 'for-generate' loop (Created page with "C++ application: <nowiki> #include "veri_file.h" #include "VeriModule.h" #include "VeriBaseValue_Stat.h" #include "VeriVisitor.h" #include "VeriExpression.h" #include "VeriC...") (current)
- 14:28, 17 November 2022 (diff | hist) . . (+79) . . Main Page
- 14:12, 28 October 2022 (diff | hist) . . (+279) . . How to save computer resources
- 16:49, 24 October 2022 (diff | hist) . . (-1) . . Replacing Verific built-in primitives/operators with user implementations (current)
- 15:27, 7 October 2022 (diff | hist) . . (0) . . Instance - Module binding order
- 16:57, 27 September 2022 (diff | hist) . . (+8) . . Modules with ' 1' ' 2' suffix in their names
- 14:12, 27 September 2022 (diff | hist) . . (+2,091) . . N Modules with ' 1' ' 2' suffix in their names (Created page with "Static elaboration process adds the suffix "_<number>" to the module name when: #Module contains hierarchical identifier(s), and #Hierarchical identifier(s) in that module poi...")
- 14:11, 27 September 2022 (diff | hist) . . (-7) . . Main Page
- 13:46, 27 September 2022 (diff | hist) . . (+7) . . Modules with " 1", " 2", ..., suffix in their names (current)
- 13:45, 27 September 2022 (diff | hist) . . (+22) . . Modules with " 1", " 2", ..., suffix in their names
- 13:44, 27 September 2022 (diff | hist) . . (-34) . . Modules with " 1", " 2", ..., suffix in their names
- 13:42, 27 September 2022 (diff | hist) . . (+676) . . Modules with " 1", " 2", ..., suffix in their names
- 12:54, 27 September 2022 (diff | hist) . . (-3) . . Modules with " 1", " 2", ..., suffix in their names
- 12:53, 27 September 2022 (diff | hist) . . (+44) . . Modules with " 1", " 2", ..., suffix in their names
- 12:52, 27 September 2022 (diff | hist) . . (+1,379) . . N Modules with " 1", " 2", ..., suffix in their names (Created page with "**** Under construction **** Static elaboration process adds the "_<number>" to the module name when: 1) Module contains hierarchical identifier(s), and 2) Hierarchical ident...")
- 12:48, 27 September 2022 (diff | hist) . . (-1) . . Main Page
- 12:47, 27 September 2022 (diff | hist) . . (+163) . . Main Page
- 23:12, 10 September 2022 (diff | hist) . . (0) . . System attributes (current)
- 23:08, 10 September 2022 (diff | hist) . . (+192) . . System attributes
- 15:45, 9 September 2022 (diff | hist) . . (+130) . . How to save computer resources
- 15:43, 9 September 2022 (diff | hist) . . (+1,133) . . How to save computer resources
- 10:08, 26 August 2022 (diff | hist) . . (+17) . . Simple example of visitor pattern
- 18:42, 24 August 2022 (diff | hist) . . (-9) . . How to tell if a module has encrypted contents (current)
- 21:59, 1 August 2022 (diff | hist) . . (0) . . Compile-time/run-time flags
- 21:52, 1 August 2022 (diff | hist) . . (+52) . . Compile-time/run-time flags
- 11:12, 19 July 2022 (diff | hist) . . (+35) . . Prettyprint all modules in the design hierarchy (current)
- 10:46, 19 July 2022 (diff | hist) . . (-8) . . Main Page
- 16:21, 12 May 2022 (diff | hist) . . (-119) . . Simple examples of VHDL visitor pattern (current)
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