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- Parsing from data in memory (14:12, 1 June 2020)
- Verilog/C++: How to get full hiererachy ID path : How to get full hiererachy ID path (12:24, 23 June 2020)
- How to get full hierarchy ID path (12:31, 23 June 2020)
- How to create new module in Verilog parsetree (13:01, 23 June 2020)
- Access attributes of ports in parsetree (14:10, 9 July 2020)
- Included files associated with a Verilog source file (17:06, 22 July 2020)
- Simulation models for Verific primitives (12:05, 4 September 2020)
- Type Range example with multi-dimensional arrays (16:07, 13 November 2020)
- Hierarchy tree RTL elaboration (15:11, 25 February 2021)
- Does Verific build CDFG? (18:10, 25 February 2021)
- Release version (18:12, 25 February 2021)
- Where in RTL is it get assigned? (13:22, 23 March 2021)
- Where in RTL does it get assigned? (22:42, 30 March 2021)
- Visiting Hierarchical References (VeriSelectedName) (12:02, 8 April 2021)
- Comment out a line using text based design modification and parsetree modification (14:17, 8 April 2021)
- Fanout cone and grouping (20:34, 18 April 2021)
- How to get library containing nested module (11:52, 19 April 2021)
- Buffering signals and ungrouping (16:11, 19 April 2021)
- Does Verific support XMR? (22:46, 20 April 2021)
- How Verific elaborator handles blackboxes/unknown boxes (16:00, 21 April 2021)
- Tcl library path (10:46, 27 April 2021)
- How to detect multiple-clock-edge condition in Verilog parsetree (10:27, 11 June 2021)
- Defined macros become undefined - MFCU vs SFCU (10:33, 11 June 2021)
- Accessing and evaluating module's parameters (13:14, 27 July 2021)
- How to get driving net of an instance (18:40, 12 August 2021)
- How to get all Verilog files being analyzed (08:57, 20 October 2021)
- How to traverse scope hierarchy (14:45, 26 October 2021)
- Statically elaborate with different values of parameters (12:38, 27 October 2021)
- Black box, empty box, and unknown box (15:45, 4 March 2022)
- Preserving user nets - preventing nets from being optimized away (11:17, 1 April 2022)
- How to ignore certain modules while analyzing input RTL files (09:26, 14 April 2022)
- Access attributes in parsetree (14:22, 3 May 2022)
- How to get packed dimensions of enum (17:46, 11 May 2022)
- Simple examples of VHDL visitor pattern (17:21, 12 May 2022)
- Prettyprint all modules in the design hierarchy (12:12, 19 July 2022)
- How to tell if a module has encrypted contents (19:42, 24 August 2022)
- System attributes (00:12, 11 September 2022)
- Python pretty-printer for gdb (11:28, 13 September 2022)
- Modules with " 1", " 2", ..., suffix in their names (14:46, 27 September 2022)
- Replacing Verific built-in primitives/operators with user implementations (17:49, 24 October 2022)
- Evaluate 'for-generate' loop (15:32, 17 November 2022)
- Verilog Port Expressions (14:40, 13 February 2023)
- How to ignore parameters/generics in elaboration (11:14, 17 February 2023)
- Compile-time/run-time flags (20:31, 2 March 2023)
- Difference between RTL and gate-level simulations - Flipflop with async set and async reset (15:02, 14 March 2023)
- Parse select modules only and ignore the rest (17:23, 5 June 2023)
- Escaped identifiers in RTL files and in Verific data structures (08:51, 16 June 2023)
- How to use RegisterPragmaRefCallBack() (12:34, 2 August 2023)
- Finding hierarchical paths of a Netlist (13:19, 22 August 2023)
- Create a Netlist Database from scratch (not from RTL elaboration) (12:20, 20 September 2023)
