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Showing below up to 48 results in range #81 to #128.

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81. Parsing from data in memory
82. Post processing port resolution of black boxes
83. Preserving user nets - preventing nets from being optimized away
84. Pretty-print a module and the packages imported by the module
85. Prettyprint all modules in the design hierarchy
86. Prettyprint to a string
87. Process -f file and explore the Netlist Database
88. Process -f file and explore the Netlist Database (C++)
89. Process -f file and explore the Netlist Database (py)
90. Python pretty-printer for gdb
91. Release version
92. Remove Verific data structures
93. Replacing Verific built-in primitives/operators with user implementations
94. Retrieve package name for user-defined variable types
95. Simple example of visitor pattern
96. Simple examples of VHDL visitor pattern
97. Simulation models for Verific primitives
98. Source code customization & Stable release services
99. Static elaboration
100. Statically elaborate with different values of parameters
101. Support IEEE 1735 encryption standard
102. SystemVerilog "std" package
103. System attributes
104. Tcl library path
105. Test-based design modification
106. Top level module with interface ports
107. Traverse instances in parsetree
108. Type Range example
109. Type Range example with multi-dimensional arrays
110. Using TypeRange table to retrieve the originating type-range for an id
111. Using stream input to ignore input file
112. VHDL, Verilog, Liberty, EDIF
113. Verific data structure
114. Verific data structures
115. Verilog/C++: How to get full hiererachy ID path : How to get full hiererachy ID path
116. Verilog/C++: How to use IsUserDeclared() : Example for port associations
117. Verilog/C++: How to use IsUserDeclared() and port associations
118. Verilog Port Expressions
119. Visiting Hierarchical References (VeriSelectedName)
120. What VeriModule* or VhdlPrimaryUnit* the Netlist comes from?
121. What are the data
122. What are the data structures in Verific?
123. What languages can I use with Verific software?
124. Where in RTL does it get assigned?
125. Where in RTL is it get assigned?
126. While looking at a Netlist
127. Why are the ports
128. Write out an encrypted netlist

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