User contributions
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- 13:18, 23 March 2021 (diff | hist) . . (+87) . . Main Page
- 17:05, 18 March 2021 (diff | hist) . . (+5) . . How to save computer resources
- 17:05, 18 March 2021 (diff | hist) . . (-1) . . How to save computer resources
- 17:04, 18 March 2021 (diff | hist) . . (+123) . . How to save computer resources
- 17:02, 18 March 2021 (diff | hist) . . (0) . . How to save computer resources
- 16:30, 18 March 2021 (diff | hist) . . (+293) . . How to save computer resources
- 18:35, 16 March 2021 (diff | hist) . . (+31) . . How to get best support from Verific
- 18:23, 16 March 2021 (diff | hist) . . (0) . . How to get best support from Verific
- 18:11, 16 March 2021 (diff | hist) . . (+127) . . How to get best support from Verific
- 18:02, 16 March 2021 (diff | hist) . . (+190) . . Escaped identifiers in RTL files and in Verific data structures
- 17:57, 16 March 2021 (diff | hist) . . (+73) . . Escaped identifiers in RTL files and in Verific data structures
- 15:15, 16 March 2021 (diff | hist) . . (+13) . . Escaped identifiers in RTL files and in Verific data structures
- 14:57, 16 March 2021 (diff | hist) . . (-4) . . Escaped identifiers in RTL files and in Verific data structures
- 14:57, 16 March 2021 (diff | hist) . . (+38) . . Escaped identifiers in RTL files and in Verific data structures
- 10:29, 16 March 2021 (diff | hist) . . (+27) . . Main Page
- 10:19, 16 March 2021 (diff | hist) . . (+201) . . Escaped identifiers in RTL files and in Verific data structures
- 10:17, 16 March 2021 (diff | hist) . . (+423) . . N Escaped identifiers in RTL files and in Verific data structures (Created page with "'''>>> This page is under construction <<<''' '''Verific data structures: ''' No escaped identifier In netlist outputs and in pretty-print outputs, identifiers are escaped b...")
- 10:11, 16 March 2021 (diff | hist) . . (+151) . . Main Page
- 10:08, 16 March 2021 (diff | hist) . . (+31) . . Main Page
- 10:07, 16 March 2021 (diff | hist) . . (+122) . . How to save computer resources
- 19:36, 15 March 2021 (diff | hist) . . (+234) . . How to save computer resources
- 15:47, 15 March 2021 (diff | hist) . . (+1,615) . . How to get linefile data of macros - Macro callback function
- 15:03, 15 March 2021 (diff | hist) . . (+7) . . Main Page
- 10:04, 15 March 2021 (diff | hist) . . (-67) . . Main Page
- 16:54, 10 March 2021 (diff | hist) . . (+8) . . How to save computer resources
- 16:51, 10 March 2021 (diff | hist) . . (+1,494) . . How to save computer resources
- 15:49, 10 March 2021 (diff | hist) . . (-10) . . Main Page
- 15:48, 10 March 2021 (diff | hist) . . (+252) . . N How to save computer resources (Created page with "'''This page is under construction. ''' - Compile flag VERIFIC_MEMORY_MANAGER - Compile flag DB_USE_PORT_ORDERED_PORTREF - Compile flag VERILOG_QUICK_PARSE_V_FILES - Run...")
- 15:40, 10 March 2021 (diff | hist) . . (+80) . . Main Page
- 17:06, 4 March 2021 (diff | hist) . . (-54) . . Message handling
- 18:12, 25 February 2021 (diff | hist) . . (+14) . . Release version (current)
- 18:11, 25 February 2021 (diff | hist) . . (-2) . . Message handling
- 18:11, 25 February 2021 (diff | hist) . . (-1) . . Message handling
- 18:10, 25 February 2021 (diff | hist) . . (+29) . . Does Verific build CDFG? (current)
- 18:09, 25 February 2021 (diff | hist) . . (+11) . . Does Verific support XMR?
- 15:14, 25 February 2021 (diff | hist) . . (+123) . . Does Verific support XMR?
- 15:11, 25 February 2021 (diff | hist) . . (+4,339) . . N Hierarchy tree RTL elaboration (Created page with "Reference: [https://www.verific.com/faq/index.php?title=Does_Verific_support_XMR%3F Does Verific support XMR?] Synthesizing designs with cross-module referencing needs Hierar...") (current)
- 15:06, 25 February 2021 (diff | hist) . . (+99) . . Main Page
- 21:37, 24 February 2021 (diff | hist) . . (+6) . . How to get best support from Verific
- 18:33, 23 February 2021 (diff | hist) . . (+113) . . Compile-time/run-time flags
- 21:11, 22 February 2021 (diff | hist) . . (+336) . . Replacing Verific built-in primitives/operators with user implementations
- 17:43, 22 February 2021 (diff | hist) . . (-51) . . Replacing Verific built-in primitives/operators with user implementations
- 16:54, 22 February 2021 (diff | hist) . . (+3,480) . . N Replacing Verific built-in primitives/operators with user implementations (Created page with "Below is a C++ application illustrating how to replace Verific's built-in primitives/operators with user implementations. <nowiki> #include <iostream> #include "veri_file.h...")
- 16:39, 22 February 2021 (diff | hist) . . (+170) . . Main Page
- 11:01, 19 February 2021 (diff | hist) . . (+190) . . How to get best support from Verific
- 10:34, 18 February 2021 (diff | hist) . . (+4) . . How to get best support from Verific
- 10:34, 18 February 2021 (diff | hist) . . (+4) . . How to get best support from Verific
- 10:33, 18 February 2021 (diff | hist) . . (+9) . . How to get best support from Verific
- 14:42, 8 February 2021 (diff | hist) . . (-65) . . Release version
- 14:02, 1 February 2021 (diff | hist) . . (+3,820) . . N How to traverse scope hierarchy (Created page with "C++ code: <nowiki> #include <iostream> #include <cstring> // strchr #include "veri_file.h" #include "VeriModule.h" #include "VeriExpression.h" #include "VeriConstVal.h" #inc...")
- 13:54, 1 February 2021 (diff | hist) . . (+85) . . Main Page
- 11:54, 1 February 2021 (diff | hist) . . (+99) . . Tcl library path
- 15:50, 27 January 2021 (diff | hist) . . (+16) . . How to get best support from Verific
- 15:49, 27 January 2021 (diff | hist) . . (-30) . . How to get best support from Verific
- 22:16, 26 January 2021 (diff | hist) . . (+33) . . How to get best support from Verific
- 22:15, 26 January 2021 (diff | hist) . . (+1) . . How to get best support from Verific
- 22:14, 26 January 2021 (diff | hist) . . (+33) . . How to get best support from Verific
- 22:12, 26 January 2021 (diff | hist) . . (0) . . How to get best support from Verific
- 22:11, 26 January 2021 (diff | hist) . . (+39) . . How to get best support from Verific
- 22:10, 26 January 2021 (diff | hist) . . (+227) . . How to get best support from Verific
- 18:59, 26 January 2021 (diff | hist) . . (+138) . . How to get linefile data of macros - Macro callback function
- 18:05, 26 January 2021 (diff | hist) . . (+9,714) . . N How to get linefile data of macros - Macro callback function (Created page with "C++ application: <nowiki> #include <iostream> #include <sstream> #include "veri_file.h" #include "VeriTreeNode.h" #include "Map.h" using namespace std ; #ifdef VERIFIC_N...")
- 18:01, 26 January 2021 (diff | hist) . . (+148) . . Main Page
- 20:20, 7 January 2021 (diff | hist) . . (+10) . . Difference between RTL and gate-level simulations - Flipflop with async set and async reset
- 20:18, 7 January 2021 (diff | hist) . . (-2) . . Difference between RTL and gate-level simulations - Flipflop with async set and async reset
- 15:38, 7 January 2021 (diff | hist) . . (-1) . . Difference between RTL and gate-level simulations - Flipflop with async set and async reset
- 15:36, 7 January 2021 (diff | hist) . . (-3) . . Difference between RTL and gate-level simulations - Flipflop with async set and async reset
- 15:21, 7 January 2021 (diff | hist) . . (+6) . . Difference between RTL and gate-level simulations - Flipflop with async set and async reset
- 15:19, 7 January 2021 (diff | hist) . . (-2) . . Difference between RTL and gate-level simulations - Flipflop with async set and async reset
- 15:15, 7 January 2021 (diff | hist) . . (-98) . . Difference between RTL and gate-level simulations - Flipflop with async set and async reset
- 15:15, 7 January 2021 (diff | hist) . . (+5,337) . . N Difference between RTL and gate-level simulations - Flipflop with async set and async reset (Created page with "'''Difference between RTL and gate-level simulations - Flipflop with async set and async reset''' ''This article is inspired by an article by Clifford E. Cummings and Don Mil...")
- 15:04, 7 January 2021 (diff | hist) . . (+192) . . Main Page
- 13:34, 23 December 2020 (diff | hist) . . (-10) . . Verilog Port Expressions
- 13:33, 23 December 2020 (diff | hist) . . (+10) . . Verilog Port Expressions
- 11:26, 23 December 2020 (diff | hist) . . (+40) . . How Verific elaborator handles blackboxes/unknown boxes
- 10:45, 23 December 2020 (diff | hist) . . (+10) . . How Verific elaborator handles blackboxes/unknown boxes
- 10:00, 23 December 2020 (diff | hist) . . (+861) . . How Verific elaborator handles blackboxes/unknown boxes
- 23:52, 22 December 2020 (diff | hist) . . (-9) . . Black box, empty box, and unknown box
- 23:51, 22 December 2020 (diff | hist) . . (-14) . . How Verific elaborator handles blackboxes/unknown boxes
- 23:50, 22 December 2020 (diff | hist) . . (+14) . . How Verific elaborator handles blackboxes/unknown boxes
- 23:48, 22 December 2020 (diff | hist) . . (+142) . . Black box, empty box, and unknown box
- 23:46, 22 December 2020 (diff | hist) . . (+63) . . How Verific elaborator handles blackboxes/unknown boxes
- 18:45, 22 December 2020 (diff | hist) . . (+3,431) . . N How Verific elaborator handles blackboxes/unknown boxes (Created page with ">> This page is in progress << '''Q: After RTL elaboration on a Verilog design, I see Netlist with names such as 'NamedPorts' or 'OrderedPorts.' Sometimes in the Verilog netl...")
- 18:22, 22 December 2020 (diff | hist) . . (+129) . . Main Page
- 18:18, 22 December 2020 (diff | hist) . . (+10) . . Black box, empty box, and unknown box
- 17:32, 7 December 2020 (diff | hist) . . (+1,033) . . N Simple example of visitor pattern (Created page with " <nowiki> $ cat test.cpp #include <iostream> #include "veri_file.h" #include "VeriModule.h" #include "VeriVisitor.h" #include "VeriConstVal.h" #include "Strings.h" #ifdef V...")
- 17:29, 7 December 2020 (diff | hist) . . (+89) . . Main Page
- 13:49, 7 December 2020 (diff | hist) . . (+2,605) . . N Access attributes in parsetree (Created page with " <nowiki> #include "veri_file.h" #include "VeriModule.h" #include "VeriExpression.h" #include "VeriMisc.h" #include "VeriId.h" #include "Map.h" #include "Array.h" #include "...")
- 13:45, 7 December 2020 (diff | hist) . . (+90) . . Main Page
- 13:18, 7 December 2020 (diff | hist) . . (+242) . . Message handling
- 23:14, 17 November 2020 (diff | hist) . . (+224) . . How to get best support from Verific
- 16:09, 13 November 2020 (diff | hist) . . (+5) . . Main Page
- 16:07, 13 November 2020 (diff | hist) . . (+5,187) . . Type Range example with multi-dimensional arrays (current)
- 15:45, 7 October 2020 (diff | hist) . . (+22) . . LineFile data from input files
- 15:15, 1 October 2020 (diff | hist) . . (+2,137) . . N LineFile data from input files (Created page with "Verific uses the 'LineFile' manager to preserve line/file origination information from HDL source files. This info is annotated on all objects in parse trees and netlist datab...")
- 15:04, 1 October 2020 (diff | hist) . . (+70) . . Main Page
- 14:20, 15 September 2020 (diff | hist) . . (+8) . . How to get best support from Verific
- 12:05, 4 September 2020 (diff | hist) . . (+5) . . Simulation models for Verific primitives (current)
- 12:04, 4 September 2020 (diff | hist) . . (+98) . . N Simulation models for Verific primitives (Created page with "They are in example_designs/verilog/verificmodels.v and example_designs/verilog/verificsvamodels.v")
- 12:03, 4 September 2020 (diff | hist) . . (+143) . . Main Page
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