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Archives for April 2011

4 April 2011

Ausdia Licenses Verific’s Parser Platform

Ausdia Inc., provider of chip design and closure solutions, has licensed Verific Design Automation’s Verilog parser platform for use with its analysis and optimization software for accelerating timing constraint development, constraint validation and timing closure.”When we looked for a platform for RTL analysis, we quickly realized that the only answer was Verific,” says Sam Appleton, Ausdia’s chief executive officer (CEO).

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