Verific's Parser Platform
  • SystemVerilog IEEE 1800-2005 / 2009 / 2012 parser, analyzer, and elaborators

  • VHDL IEEE 1076-1993 / 2002 / 2008 parser, analyzer, and elaborators

  • UPF IEEE 1801-2009 / 2013 parser and analyzer

  • Full mixed SystemVerilog / VHDL language support

  • Verilog IEEE 1364-1995 / 2001 / 2005 pre-processor, parser, analyzer, and elaborators

  • Verilog-AMS 2.3 parser and analyzer

  • Verilog netlist only parser

  • EDIF 2.0, SDF, Liberty parsers and analyzers

  • SystemVerilog

  • Verilog 2001

  • Verilog-AMS
HDL Language Synthesis

Verific Design Automation builds SystemVerilog, VHDL, and UPF Parser Platforms which enable its customers to develop advanced EDA products quickly and at low cost. Verific's Parser Platforms are distributed as C++ source code and compile on all 32 and 64 bit Unix, Linux, and Windows operating systems. Verific's Parser Platforms are in production and development use today at numerous companies worldwide, from EDA start-ups to established Fortune 500 semiconductor vendors. Applications vary from formal verification to synthesis, simulation, emulation, virtual prototyping, in circuit debug, and design-for-test.

To view some of the EDA products you can find us in, click here.


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