Booth 2141

• SystemVerilog IEEE 1800-2005 / 2009 parser, analyzer, and elaborators
  
  
• VHDL IEEE 1076-1993 / 2002 / 2008 parser, analyzer, and elaborators
  
  
• Verilog IEEE 1364-1995 / 2001 / 2005 pre-processor, parser, analyzer, and elaborators
  
  
• Full mixed SystemVerilog / VHDL language support
  
  
• UPF IEEE 1801-2009 parser and analyzer
  
  
• Verilog-AMS 2.3 parser and analyzer
  
  
• PSL IEEE 1850 parser and analyzer for VHDL and Verilog
  
  
• EDIF 2.0, SDF, Liberty parsers and analyzers
  
  
• Hierarchical, technology independent database
  
  
• Verilog netlist only parser
  
  

• SystemVerilog



• Verilog 2001



• Verilog-AMS

Verific Design Automation builds SystemVerilog and VHDL Parser Platforms which enable its customers to develop advanced EDA products quickly and at low cost. Verific's Parser Platforms are distributed as C++ source code and compile on all 32 and 64 bit Unix, Linux, and Windows operating systems. Verific's Parser Platforms are in production and development use today at numerous companies worldwide, from EDA start-ups to established Fortune 500 semiconductor vendors. Applications vary from formal verification to synthesis, simulation, emulation, virtual prototyping, in circuit debug, and design-for-test.

Some of the products you find us in are:

COMPANY	PRODUCT
Achronix	ACE
Aldec	HES
Altera	Quartus II
Altium	Nexar
Apache	Power Theater Power Artist
Ausdia	TimeVision
Axiom	@Verifier
Blue Pearl	Blue Pearl Software Suite
Calypto	SLEC, PowerPro
CLKDA	Amber
Concept Engineering	RTLVision PRO
DeFacTo	STAR, SIGNOFF
EVE	ZeBu
Excellicon	ConMan
Forte	CellMath Designer
HDL Works	HDL Companion
Infineon	Inway
iRoC	SoCFIT
Jasper	JasperGold
Lattice	ispLEVER
Magma	FineSim Quartz Formal
Microsemi	Libero
NEC	CyberWorkBench
NextOp	Bugscope
NXP Semiconductor	RTL DfT
Oasys	RealTime Designer
Parallel Engines	IP/RTL floorplanner
Real Intent	Ascent, Meridian
Rocketick	RocketSim
S2C	TAI IP
Springsoft	Certitude
Synopsys	CHIPit MVSIM
Tektronix	Clarus
Tiempo	ACC
Vennsa	OnPoint
vSync Circuits	vChecker
Xilinx	ISE Design Suite

"We have employed Verific's SystemVerilog parser for several years within our internally developed EDA tools."

— Dan Smith, senior director, hardware engineering, NVIDIA

• Verific increases revenue by 20%

• Aldec partners with Verific for HES platform

• Excellicon's ConMan uses Verific

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