• SystemVerilog IEEE 1800 parser, analyzer, and elaborator



• VHDL IEEE 1076-1993
  parser, analyzer, and elaborator



• Verilog IEEE 1364-1995/2001
  pre-processor, parser, analyzer, and elaborator



• Verilog-AMS parser and analyzer



• PSL/SUGAR parser and analyzer for VHDL and Verilog



• EDIF 2.0 Reader



• SDF Reader



• Liberty Reader



• Hierarchical, technology independent database

• SystemVerilog



• Verilog 2001



• Verilog-AMS

Verific Design Automation Inc. develops and sells source code (C++) Verilog, SystemVerilog, and VHDL front-ends (parsers, analyzers, elaborators) as well as a generic hierarchical netlist database for EDA applications.

Many EDA and semiconductor companies worldwide are shipping products incorporating Verific's Verilog and VHDL technology, with a combined customer base of over 40,000 users. Applications include RTL simulation, FPGA synthesis, Model Checking, Functional Verification, Hardware Acceleration, RTL Debug, Logic Equivalence Checking, RTL Floorplanning, HDL Entry, and Design for Test. Some of the products you find us in are:

• SystemVerilog Leaps From 2005 To 2009, And Beyond

• Verific used as front-end to Oasys' RealTime Designer

• Tiempo Chooses Verific's SystemVerilog