Verific Design Automation, with offices in Kolkata, India and Alameda, CA, was founded in 1999 by EDA industry veteran Rob Dekker. Prior to founding Verific, Dekker was a software developer, manager and director at Exemplar Logic.
As a leading provider of SystemVerilog, VHDL, and UPF front-ends, Verific’s software is used worldwide in synthesis, simulation, formal verification, emulation, debugging, virtual prototyping and design-for-test applications, which combined have shipped over 60,000 copies.
Please contact us to discuss your requirements