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Archives for May 2019

29 May 2019

Verific, 20 Years Terrific

What do JasperGold, Stratus, and the Rocketick part of Xcelium have in common? Well, they are all Cadence products, of course. But they also all use Verific as parsers for SystemVerilog, Verilog, and VHDL.

Verific got started twenty years ago, Rob Dekker told me.

Read more at Cadence Breakfast Bytes Blog.

Filed Under: Geen categorie

Design Automation Conference

Rick Carlson at DAC 2017
Interview with Rick Carlson, VP of Sales, at DAC 2018

DAC interview video
Interview with Rob Dekker at DAC 2016

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