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Archives for October 2016

10 October 2016

Verific: the Name is Short for Verification…

I had an interesting conversation with Michiel Ligthart and Rick Carlson of Verific. They have a unique niche in the EDA ecosystem. They provide parsers for SystemVerilog, VHDL, and IEEE 1801 (fka UPF). They really have no competition other than companies that develop their own parsers in-house, usually for historical reasons.

Read more at Cadence.com

Filed Under: Geen categorie

Design Automation Conference

Rick Carlson at DAC 2017
Interview with Rick Carlson, VP of Sales, at DAC 2018

DAC interview video
Interview with Rob Dekker at DAC 2016

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