Verific’s Verilog parser supports the entire IEEE-1164 standard (1995, 2001) and can be extended with Verilog-AMS 2.4.
- The parser is compatible with leading industry simulators Incisive, QuestaSim, and VCS.
- The parser supports static elaboration as well as RTL elaboration, and is integrated with a language-independent netlist data structure common to all parsers.
- RTL elaboration supports all synthesis pragma’s and is compatible with leading synthesis tools such as Design Compiler, RTL Compiler, Synplify, and Precision.
- Users interface with the parse tree or netlist data structures through an extensive set of APIs in C++, Perl, or Python.