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VHDL

Verific’s VHDL parser supports the entire IEEE-1076 standard (2019, 2008, 1993, 1987) for analysis, and is compatible with leading industry simulators Xcelium, QuestaSim, and VCS.

  • The parser supports static elaboration as well RTL elaboration, and is integrated with a language-independent netlist data structure common to all parsers.
  • RTL elaboration supports all synthesis pragma’s and is compatible with leading synthesis tools such as Design Compiler, RTL Compiler, Synplify, and Precision.
  • Users interface with the parse tree or netlist data structures through an extensive set of APIs in C++, Perl, or Python.

VHDL with white background

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Highlights

  • Supports all of VHDL IEEE 1076
  • Specialized packages for mixed -1993 / -2008 support
  • 100% language coverage for analysis
  • Static and RTL elaboration modules
  • Mixed language with SystemVerilog fully supported
  • Preservation of line/file/column origination into database
  • Shipped as C++ source code
  • SystemVerilog
  • VHDL
  • UPF
  • INVIO
  • Verilog
  • Verilog-AMS
  • Verilog Netlist Only
  • EDIF / SDF / Liberty
  • Verilog Test Suites
  • Back to Main Flow Diagram

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Verific Design Automation, Inc.
Please call (+1) 510-522-1555
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