Verific Design Automation today confirmed its Parser Platform serves as the front end to Symbiotic EDA’s system-on-chip (SoC) synthesis, formal verification and field programmable gate array (FPGA) chip design software.
The six-part series of interviews with some of Verific’s biggest user fans concludes with profiles of Wolfgang Roesner, IBM Fellow for Hardware Verification and Verification Tools, and serial entrepreneur George Janac.
Going the Extra Mile
ANSYS Semiconductor’s Vic Kulkarni, who serves as its vice president and chief strategist, offers a fitting tribute to Verific. “Verific goes the extra mile and provides solutions head and shoulders above others.”
Good Partnership on All Levels
A profile of Verific’s partnership with Real Intent is the next post in the series. Rajiv Kumar, its vice president of engineering, details the relationship between the two companies. As far as he’s concerned, there’s no need to look at another vendor.
The Silent Partner
The blog post series resumes with Andrew Dauman, vice president of engineering at Tortuga Logic, who considers Verific to be a silent partner. Verific’s impact on the industry has never been visible, but it’s significant, nonetheless.
Marrying Expertise to Avoid Redoing What’s Already Been Done
The blog post series continues with Baum’s Andy Ladd who values the Verific relationship. Verific’s marries its customers’ expertise with its own to avoid redoing what’s already been done.
Fierce Loyalty to Verific’s Value
An interview with Scott Aron Bloom, former chief technology officer at Blue Pearl and a 17-year Verific customer, is perhaps the best way to kick-off the blog post series. “I’m fiercely loyal and value what Verific provides.”
Six Short Interviews with Some of Verific’s Long-Time Customers Highlight Positive Experience
Nanette Collins, public relations consultant for Verific, interviewed several of Verific’s long-time customers and wrote a six-part blog series on their experience with Verific.
Verific Design Automation today announced long-time customer vSync Circuits added Verific’s static elaboration to its product mix and introduced vLinter, early rule-based design analysis and verification software.
What do JasperGold, Stratus, and the Rocketick part of Xcelium have in common? Well, they are all Cadence products, of course. But they also all use Verific as parsers for SystemVerilog, Verilog, and VHDL.
Verific got started twenty years ago, Rob Dekker told me.