Verific Design Automation, the tool development specialist, and its R&D and applications staff will be at the exhibition during the Design Automation Conference (DAC) in San Francisco next week (Booth #1415).
An internal computer aided design (CAD) or design services engineer is responsible for delivering efficient, robust and high-quality design flow solutions. The design flow on a day-to-day basis keeps chip designers and verification engineers productive and focused on their jobs, preventing them from debugging CAD tools and flows and creating ad hoc and undocumented scripts. Over the life of a project, a high-quality design flow differentiates a company from competitors and can be the difference between getting chips to market first or being the victim of unexpected process bottleneck and delays.
Verific is an unusual company. They are completely dominant in what they do – providing parsers for Verilog/SV, VHDL and UPF. Yet they have no ambition to expand beyond that goal. Instead, per Michiel Ligthart (President and COO), they continue to “sharpen the saw”. This is an expression I learned in sales training, habit #7 from 7 Habits of Highly Effective People. Constantly refining and polishing (or sharpening) the tools you already have rather than launching out into building new tools. That’s a great way to keep existing customers loyal and to steadily grow a business. They are still investing in interesting development, but it is all around these core tools.
Verific Design Automation, the leading provider of SystemVerilog, Verilog, VHDL and UPF Parser Platforms, today announced Rapid Silicon, a provider of AI-enabled application-specific FPGAs based on open-source technology, is the newest licensee of its Parser Platform.
To gain at least an 18 month advantage in getting a product to market, Verific Design Automation builds SystemVerilog, UPF and VHDL parser platforms which accelerates the production cycle because the RTL front end is immediately accepted by the semiconductor industry, says the company.
Michiel Ligthart | President and COO | Verific Design Automation
Conventional career advice favors “playing to your strength,” guidance executives at Apple, Amazon, Facebook, Microsoft and Tesla may have missed. Instead, they are charging ahead in the chip development business, a new market segment for all of them. What may seem foolhardy to some industry watchers could be a stroke of genius as their development groups design higher performing, power-efficient computer chips for their specific networking, cloud, automotive and other applications.
To do so, they are hiring experienced, seasoned designers who know the ropes. Whether intentional or not, they are focusing on a development group’s core competencies (aka “playing to your strength”) and outsourcing the rest, a sound strategic business decision.
Alameda, Calif.-based Verific Design Automation, a member of the ESD Alliance, made its name in the electronic system design and semiconductor industry supporting companies ranging from startups to billion-dollar industry leaders such as Synopsys, Cadence, Siemens EDA, Xilinx, Microchip, NVidia, Infineon, Qualcomm, Renesas and Samsung. Its software is used as the front end to design automation tools such as synthesis, simulation, debug, and formal verification.
I spoke with Verific president and COO Michiel Ligthart about homegrown and open-source EDA tools and other recent trends in chip design.
By Rick Carlson, Verific Design Automation
The makeup of the semiconductor industry is evolving and expanding once again. This time it’s a variety of companies, including tech giants Apple, Amazon, Facebook, Microsoft and Tesla, not known previously to be in the chip development business, instigating the change. They are hiring experienced engineers to design better performing, power-efficient computer chips for all kinds of applications, from networking and cloud to autonomous driving. Along the way, they are ripping up the pages of the traditional semiconductor playbook and putting in place their own individual guides to semiconductor design. The result is custom-made chips rather than using a generic chip to fit their requirements.
“Continuous education starts during hiring with a well-ordered training program,” says Abhijit Chakrabarty, general manager for India operations at Verific, for Semiconductor Engineering’s article on Continuous Education for Engineers. “We don’t expect new hires to be experts in SystemVerilog, C++, compiler technology, and digital design.
“We often engage with students as summer trainees,” says Chakrabathy. “Initially, they are provided with LRMs of the SystemVerilog and/or VHDL language, and they play with simulators and in-house designs. They are then introduced to the concept of synthesizable designs. After six to eight months, they are tasked with writing applications using defined APIs while following a strict coding guideline. During the entire training process, all senior members of the technical staff are available for guidance and help with technical queries. When developing core software, senior developers are there to provide code reviews and lots of feedback. The whole lifecycle is continuous learning.”
Today, Semiwiki profiles Verific Design Automation, perhaps the most popular company at DAC (when it’s an in-person event) because of its giveaway –– a 10”stuffed giraffe for anyone who walks up to its booth and listens to its story.
But, Verific is also a popular EDA company for more reasons than its tradeshow giveaway. If you’re using any type of FPGA implementation or EDA verification tool, Verific is probably inside.