Ann Wu is CEO of EDA startup Silimate, developer of a co-pilot (chat-based GenAI) for chip and IP designers to find and fix functional and power, performance and area (PPA) issues in their designs. Rick Carlson is Vice President of Sales at ESD Alliance member company Verific Design Automation, provider of front-end EDA platforms to a range of small and emerging EDA companies like Silimate and larger EDA vendors.

I recently talked with Ann and Rick who represent EDA’s new and old guard. I found them to be bullish about the emerging EDA space called AI EDA that uses GenAI and large language models as the foundational tools and the swelling numbers of well-funded startups entering this space.

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Rick Carlson, Verific Design Automation’s Vice President of Sales, is an EDA trends spotter. I was reminded of his prescience when he recently called to catch up and talk about Verific’s role as provider of front-end platforms powering an emerging EDA market.

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2024 marks Verific’s 25th anniversary as a valued supplier of front-end Parser Platforms! Rob Dekker, our founder, president and CTO, and COO Michiel Ligthart talk with Bob Smith, the ESD Alliance’s Executive Director, about our evolution and the industry over the last 25 years and what’s to come.

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“While the big EDA vendors talked about using AI to tackle all the chip design complexity, it was also refreshing to see some (well-funded) startups starting to tackle EDA industry challenges using generative AI. I spoke to Rick Carlson, a veteran of the EDA industry (he told me this was his 40th year), and he suggested the emergence of these new EDA startups was an exciting new phase of the EDA industry – maybe, what I like to call it, EDA 3.0. He highlighted two of those whom I also spoke to, which were Silimate, and PrimisAI.”

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• AI EDA newcomers Metalware, PrimisAI, Silimate, stealth-mode startup latest Verific Users
• Verific’s unsurpassed language support used for fast, accurate LLM development

ALAMEDA, CALIF. –– June 19, 2024 –– Verific Design Automation today affirmed its position as the leading provider of front-end platforms powering an emerging electronic design automation (EDA) space by collaborating with a group of well-funded artificial intelligence (AI) EDA startups.

These new AI EDA companies use Verific’s unsurpassed language support for fast, accurate large language model (LLM) development, speeding time to market for products that range from functional verification, chip design to code development.

AI EDA providers PrimisAI and Silimate, founded by former chip designers, will be in the Verific booth (#1414) AI showcase at the 61st Design Automation Conference (DAC) June 24-26 at Moscone West in San Francisco.

“This new and exciting market segment is about to change the entire makeup of the EDA industry,” says Rick Carlson, vice president of Verific. “We are about to see a variety of tools, technologies and methodologies destined to change the way chip design and verification is done.”

Introducing the EDA Startups Ushering in the Era of AI EDA

PrimisAI and Silimate will be showcased in the Verific DAC booth and present their unique use of AI technology to eliminate error-prone repetitive tasks for efficient and more productive chip design.

PrimisAI offers a generative AI solution for chip design with advanced language-to-code and language-to-verification capabilities through its interactive AI assistant to address complex hardware challenges across the entire design stack from concept to bitstream/GDSII. RapidGPT, unveiled earlier this year, lets engineers interact with their design and the entire EDA ecosystem with a natural language interface, boosting productivity and accelerating time-to-market. Founded by serial entrepreneur Naveed Sherwani who serves as chairman and CEO, PrimisAI is backed by two early-stage investors.

“Verific’s front-end platform lived up to its well-earned status of industry standard as we implemented it in RapidGPT,” remarks Pierre-Emmanuel Gaillardon, CSO of PrimisAI. “The robustness and quality of the Verific front-end platform ensured we would deliver a tool that would give engineers a seamless and efficient workflow.”

Silimate, backed by Y Combinator, is building the co-pilot for chip designers to help build better chips faster. Silimate finds functional bugs, predicts power, performance and area (PPA) issues, and recommends real and accurate fixes in real time, and is already being used by chip teams building complex IP and SoCs. Co-founders Ann Wu and Akash Levy previously built chips and EDA tools at Apple, Stanford, NVIDIA, and Synopsys.

“Verific consistently produces quality products and offers exceptional quality support,” comments Wu. “Their parsers are fantastic and result in very quick tool bring-up times for our customers.”

Metalware co-founded by Ryan Chow and Andrew Nedea is another Verific front-end platform user. It was started with initial funding from Y Combinator with the mission to accelerate embedded development using AI technology after personally experiencing repeated bottlenecks in embedded software at SpaceX. The Metalware AI EDA tools help designers rapidly write HDL and embedded C/C++ by combining insights from manuals, datasheets and code, offering 10x faster development by automating low-level programming.

“Verific embodies our stated goals to reduce the time it takes to design chips and systems,” affirms Chow. “Verific and its team of experienced EDA engineers have shown repeatedly that its front-end platforms enable a project that would normally take days to be completed in hours.” Another AI EDA startup in stealth mode is also a new Verific user. Details will be announced shortly.

DAC AI Showcase

Verific will demonstrate its SystemVerilog, Verilog, VHDL and UPF front-end platforms, while PrimisAI and Silimate will be in the Verific DAC Booth #1414 at various times of the day to give 10-minute presentations.

DAC will be held from Monday, June 24, through Wednesday, June 26, from 10 a.m. until 6 p.m. at Moscone West in San Francisco.

To arrange a demonstration or private meeting, send email to info@verific.com

DAC registration is open.

About Verific Design Automation

Verific Design Automation is the leading provider of SystemVerilog, Verilog, VHDL and UPF Parser Platforms that enable project groups to develop advanced electronic design automation (EDA) products quickly and cost effective worldwide. With offices in Alameda, Calif., and Kolkata, India, Verific has shipped more than 60,000 copies of its software used worldwide by the EDA and semiconductor industry since it was founded in 1999.

Engage with Verific at:

Email: info@verific.com

Website: www.verific.com

LinkedIn: https://www.linkedin.com/company/verific-design-automation-inc/

Facebook: https://www.facebook.com/Verific-Design-Automation-100448363329771/

Verific Design Automation acknowledges trademarks or registered trademarks of other organizations for their respective products and services. Approved for Public Release, Distribution Unlimited.

The partnership Rick forged with Illinois Tech is an inspiring story of ways individuals can get involved in helping the semiconductor industry’s professional development programs at the college level.

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A blog post on Semiwiki profiling Rick Carlson.

The concept of giving back is something many of us have contemplated. Giving back to the community or to support a particular cause. How to respond to those inquiries from our alma mater is another example.

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Verific’s HDL parser platform was used by Vorak Solutions, providers of high-quality development and quality assurance services for software, cloud and EDA products, to create a new synthesis flow for Rapid Silicon’s FPGA design suite. The result? A high-performance synthesis tool with 2X better performance

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Coming full or almost full circle to a by-gone era of specialized CAD flows

For so long, designers used off-the-shelf electronic design automation (EDA) tools from major players, startups and technology companies somewhere in between the two to get their chips produced. It’s been a long-accepted practice that’s shifting to a strategy where the watchwords are proprietary, customized and differentiated.

It started as well-respected semiconductor companies began moving processor design in-house to realize better cost-effectiveness, eliminate the middleman and, most importantly, differentiate their products from their competitors by implementing a proprietary environment. They built portfolios of proprietary intellectual property (IP) customized and differentiated from their competitors, producing high-performing, power-efficient computer chips for autonomous driving, cloud, 5G, networking and other applications. Now comes “bespoke EDA,” a derivative of bespoke silicon and a hybrid strategy taking hold throughout the world of chip design.

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Vorak’s Verific Parser Platform Knowledge and Engineering Assist Verific Customers

Verific Design Automation today announced Vorak Solutions is its vendor of choice to assist Verific customers to accelerate projects that implement its SystemVerilog, Verilog, VHDL and UPF Parser Platforms.

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