Verific’s HDL parser platform was used by Vorak Solutions, providers of high-quality development and quality assurance services for software, cloud and EDA products, to create a new synthesis flow for Rapid Silicon’s FPGA design suite. The result? A high-performance synthesis tool with 2X better performance

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Coming full or almost full circle to a by-gone era of specialized CAD flows

For so long, designers used off-the-shelf electronic design automation (EDA) tools from major players, startups and technology companies somewhere in between the two to get their chips produced. It’s been a long-accepted practice that’s shifting to a strategy where the watchwords are proprietary, customized and differentiated.

It started as well-respected semiconductor companies began moving processor design in-house to realize better cost-effectiveness, eliminate the middleman and, most importantly, differentiate their products from their competitors by implementing a proprietary environment. They built portfolios of proprietary intellectual property (IP) customized and differentiated from their competitors, producing high-performing, power-efficient computer chips for autonomous driving, cloud, 5G, networking and other applications. Now comes “bespoke EDA,” a derivative of bespoke silicon and a hybrid strategy taking hold throughout the world of chip design.

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Vorak’s Verific Parser Platform Knowledge and Engineering Assist Verific Customers

Verific Design Automation today announced Vorak Solutions is its vendor of choice to assist Verific customers to accelerate projects that implement its SystemVerilog, Verilog, VHDL and UPF Parser Platforms.

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Michiel Ligthart on 10-26-2022

When I first heard the term ‘bespoke silicon,’ I had to get my dictionary out. Well versed in the silicon domain, I did not know what bespoke meant. It turns out to be a rather old-fashioned term for tailor made and seems to be very much British English. The word dates from 1583 and is the past participle of bespeak, according to the Oxford English Dictionary. American English by contrast more commonly uses the word custom. By now, custom silicon has been rebranded to bespoke silicon.

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Illinois Institute of Technology (Illinois Tech) alumnus Rick Carlson (MATH ’70), vice president of sales for Verific Design Automation, a leading provider of SystemVerilog, Verilog, VHDL, and UPF Parser Platforms, has been elected to the College of Computing Board of Advisors.

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Verific Design Automation, the tool development specialist, and its R&D and applications staff will be at the exhibition during the Design Automation Conference (DAC) in San Francisco next week (Booth #1415).

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An internal computer aided design (CAD) or design services engineer is responsible for delivering efficient, robust and high-quality design flow solutions. The design flow on a day-to-day basis keeps chip designers and verification engineers productive and focused on their jobs, preventing them from debugging CAD tools and flows and creating ad hoc and undocumented scripts. Over the life of a project, a high-quality design flow differentiates a company from competitors and can be the difference between getting chips to market first or being the victim of unexpected process bottleneck and delays.

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Verific is an unusual company. They are completely dominant in what they do – providing parsers for Verilog/SV, VHDL and UPF. Yet they have no ambition to expand beyond that goal. Instead, per Michiel Ligthart (President and COO), they continue to “sharpen the saw”. This is an expression I learned in sales training, habit #7 from 7 Habits of Highly Effective People. Constantly refining and polishing (or sharpening) the tools you already have rather than launching out into building new tools. That’s a great way to keep existing customers loyal and to steadily grow a business. They are still investing in interesting development, but it is all around these core tools.

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Verific Design Automation, the leading provider of SystemVerilog, Verilog, VHDL and UPF Parser Platforms, today announced Rapid Silicon, a provider of AI-enabled application-specific FPGAs based on open-source technology, is the newest licensee of its Parser Platform.

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To gain at least an 18 month advantage in getting a product to market, Verific Design Automation builds SystemVerilog, UPF and VHDL parser platforms which accelerates the production cycle because the RTL front end is immediately accepted by the semiconductor industry, says the company.

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