The blog post series resumes with Andrew Dauman, vice president of engineering at Tortuga Logic, who considers Verific to be a silent partner. Verific’s impact on the industry has never been visible, but it’s significant, nonetheless.
The blog post series continues with Baum’s Andy Ladd who values the Verific relationship. Verific’s marries its customers’ expertise with its own to avoid redoing what’s already been done.
An interview with Scott Aron Bloom, former chief technology officer at Blue Pearl and a 17-year Verific customer, is perhaps the best way to kick-off the blog post series. “I’m fiercely loyal and value what Verific provides.”
“2019 was the year when many people started to realize that the dream of autonomous cars on our roads is still a long way out,” says Michiel Ligthart, chief operating officer for Verific Design Automation. “Let’s be honest, what good is a technology that requires me to have my hands (sweaty palms and all) on the wheel and my foot near the brake so I can take over at any moment when the robot fails?”
Read the entire 2019 retrospective article at Semiconductor Engineering.
Verific Design Automation today announced long-time customer vSync Circuits added Verific’s static elaboration to its product mix and introduced vLinter, early rule-based design analysis and verification software.
What do JasperGold, Stratus, and the Rocketick part of Xcelium have in common? Well, they are all Cadence products, of course. But they also all use Verific as parsers for SystemVerilog, Verilog, and VHDL.
Verific got started twenty years ago, Rob Dekker told me.
I recently had a call with Rob Dekker, Founder and CTO of Verific. If you’re in EDA or semiconductor CAD, chances are high that you know who they are. They’re king of the hill in parser software for SystemVerilog and VHDL.
Sanjay Gangal interviewed Michiel Ligthart, President and COO at Verific Design Automation at the 2019 DVCon.
Verific Design Automation today announced Innergy Systems licensed its Parser Platform to serve as the front end to its new Power Analysis Platform that combines quick-debug power analysis with fast power model generation.
Verific Design Automation today announced Empyrean, provider of fast and physically aware, design closure and optimization solutions for systems on chip (SoCs), licensed its Parser Platform to function as the front end to Qualib, library quality inspection software.
Free 30-day Evaluation Package
Click here for our free Evaluation Package
PDF Downloads
Datasheets, white papers and blogs
Viper
Online defect and enhancement tracking
Documentation
Online documentation
FAQs
Q and A on Verific APIs and more
Verific Design Automation, Inc.
Please call (+1) 510-522-1555
Or email us at info@verific.com