I recently had a call with Rob Dekker, Founder and CTO of Verific. If you’re in EDA or semiconductor CAD, chances are high that you know who they are. They’re king of the hill in parser software for SystemVerilog and VHDL.
Verific celebrates 20 years
Sanjay Gangal interviewed Michiel Ligthart, President and COO at Verific Design Automation at the 2019 DVCon.
Innergy Systems Powers Up with Verific
Verific Design Automation today announced Innergy Systems licensed its Parser Platform to serve as the front end to its new Power Analysis Platform that combines quick-debug power analysis with fast power model generation.
Verific’s Parser Platform License Secured by Empyrean
Verific Design Automation today announced Empyrean, provider of fast and physically aware, design closure and optimization solutions for systems on chip (SoCs), licensed its Parser Platform to function as the front end to Qualib, library quality inspection software.
Verific Integrates INVIO with Flagship Parsers
Verific today announced full integration of INVIO with its flagship parser platforms. This follows an earlier announcement that it acquired from Invionics Software the INVIO platform, with its high-level level application programming interfaces (APIs) that enable Verific users to simplify and streamline their design environment, accelerating tool development.
Verific’s Parser Platform Selected by Efinix
Verific Design Automation today announced Efinix™, an innovator in programmable product platforms and technology, selected its Verilog Parser Platform and register transfer level (RTL) elaborator to serve as the front end to the Efinity™ Integrated Design Environment (IDE).
Baum Licenses Verific’s Parser Platform
Baum, a leader in power analysis solutions, today became the newest licensee of Verific Design Automation, the recognized leader of SystemVerilog, VHDL and UPF Parser Platforms in production and development use throughout the semiconductor industry.
Verific Acquires INVIO Platform
Under terms of the agreement, Verific will acquire Invionics Software’s entire INVIO technology portfolio, for electronic design automation (EDA) tools and flows. An R&D group with real-world design experience and a deep understanding of EDA software development will join Verific’s engineering department.
Verific signs functional safety provider Austemper
SystemVerilog and VHDL parsers from Verific serve as the front end to Austemper’s software that analyzes, augments and verifies functional safety in system-on-chip (SoC), application specific integrated circuit (ASIC) and intellectual property (IP) designs ensuring they meet functional safety requirements.
Verific Adds UPF Elaborator to Comprehensive Parser Platform Portfolio
New Functionality Broadens UPF Parser/Analyzer Capabilities
Verific Design Automation, the recognized leader of SystemVerilog, VHDL and Unified Power Format (UPF) Parser Platforms in production and development use throughout the semiconductor industry, today announced availability of its UPF Elaborator.
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