News - Verific Design Automation

2 November 2021

Playing to Your Company’s Strength to be Strategic, Differentiated, Competitive

Michiel Ligthart | President and COO | Verific Design Automation

Conventional career advice favors “playing to your strength,” guidance executives at Apple, Amazon, Facebook, Microsoft and Tesla may have missed. Instead, they are charging ahead in the chip development business, a new market segment for all of them. What may seem foolhardy to some industry watchers could be a stroke of genius as their development groups design higher performing, power-efficient computer chips for their specific networking, cloud, automotive and other applications.

To do so, they are hiring experienced, seasoned designers who know the ropes. Whether intentional or not, they are focusing on a development group’s core competencies (aka “playing to your strength”) and outsourcing the rest, a sound strategic business decision.

Homegrown EDA Tools, Open Source, Starting an EDA Company: Verific on Chip Design Trends

Alameda, Calif.-based Verific Design Automation, a member of the ESD Alliance, made its name in the electronic system design and semiconductor industry supporting companies ranging from startups to billion-dollar industry leaders such as Synopsys, Cadence, Siemens EDA, Xilinx, Microchip, NVidia, Infineon, Qualcomm, Renesas and Samsung. Its software is used as the front end to design automation tools such as synthesis, simulation, debug, and formal verification.

I spoke with Verific president and COO Michiel Ligthart about homegrown and open-source EDA tools and other recent trends in chip design.

Differentiation Through the Chip Design and Verification Flow

By Rick Carlson, Verific Design Automation

The makeup of the semiconductor industry is evolving and expanding once again. This time it’s a variety of companies, including tech giants Apple, Amazon, Facebook, Microsoft and Tesla, not known previously to be in the chip development business, instigating the change. They are hiring experienced engineers to design better performing, power-efficient computer chips for all kinds of applications, from networking and cloud to autonomous driving. Along the way, they are ripping up the pages of the traditional semiconductor playbook and putting in place their own individual guides to semiconductor design. The result is custom-made chips rather than using a generic chip to fit their requirements.

Interview for Semiconductor Engineering: Abhijit Chakrabarty

“Continuous education starts during hiring with a well-ordered training program,” says Abhijit Chakrabarty, general manager for India operations at Verific, for Semiconductor Engineering’s article on Continuous Education for Engineers. “We don’t expect new hires to be experts in SystemVerilog, C++, compiler technology, and digital design.

“We often engage with students as summer trainees,” says Chakrabathy. “Initially, they are provided with LRMs of the SystemVerilog and/or VHDL language, and they play with simulators and in-house designs. They are then introduced to the concept of synthesizable designs. After six to eight months, they are tasked with writing applications using defined APIs while following a strict coding guideline. During the entire training process, all senior members of the technical staff are available for guidance and help with technical queries. When developing core software, senior developers are there to provide code reviews and lots of feedback. The whole lifecycle is continuous learning.”

COO Interview: Michiel Ligthart of Verific

Today, Semiwiki profiles Verific Design Automation, perhaps the most popular company at DAC (when it’s an in-person event) because of its giveaway –– a 10”stuffed giraffe for anyone who walks up to its booth and listens to its story.

But, Verific is also a popular EDA company for more reasons than its tradeshow giveaway. If you’re using any type of FPGA implementation or EDA verification tool, Verific is probably inside.

18 December 2020

Verific and DARPA Sign Partnership for Streamlined Access to Industry-Standard SystemVerilog

Verific Design Automation today announced a partnership agreement with the U.S. Defense Advanced Research Projects Agency (DARPA) to provide the DARPA community access to its electronic design automation (EDA) software in production and development use throughout the semiconductor industry.

18 September 2020

Symbiotic EDA selects Verific for SystemVerilog, VHDL

Verific Design Automation today confirmed its Parser Platform serves as the front end to Symbiotic EDA’s system-on-chip (SoC) synthesis, formal verification and field programmable gate array (FPGA) chip design software.

17 February 2020

Celebrating 20 Years of Exceptional Support, Part 6

The six-part series of interviews with some of Verific’s biggest user fans concludes with profiles of Wolfgang Roesner, IBM Fellow for Hardware Verification and Verification Tools, and serial entrepreneur George Janac.

10 February 2020

Celebrating 20 Years of Exceptional Support, Part 5

Going the Extra Mile

ANSYS Semiconductor’s Vic Kulkarni, who serves as its vice president and chief strategist, offers a fitting tribute to Verific. “Verific goes the extra mile and provides solutions head and shoulders above others.”

3 February 2020

Celebrating 20 Years of Exceptional Support, Part 4

Good Partnership on All Levels

A profile of Verific’s partnership with Real Intent is the next post in the series. Rajiv Kumar, its vice president of engineering, details the relationship between the two companies. As far as he’s concerned, there’s no need to look at another vendor.