What do JasperGold, Stratus, and the Rocketick part of Xcelium have in common? Well, they are all Cadence products, of course. But they also all use Verific as parsers for SystemVerilog, Verilog, and VHDL.

Verific got started twenty years ago, Rob Dekker told me.

Read more at Cadence Breakfast Bytes Blog.

I recently had a call with Rob Dekker, Founder and CTO of Verific. If you’re in EDA or semiconductor CAD, chances are high that you know who they are. They’re king of the hill in parser software for SystemVerilog and VHDL.

Read more at SemiWiki.com.

Sanjay Gangal interviewed Michiel Ligthart, President and COO at Verific Design Automation at the 2019 DVCon.

Watch the video at EDAcafe.com.

Verific Design Automation today announced Innergy Systems licensed its Parser Platform to serve as the front end to its new Power Analysis Platform that combines quick-debug power analysis with fast power model generation.

Read more at EDACafe.com.

Verific Design Automation today announced Empyrean, provider of fast and physically aware, design closure and optimization solutions for systems on chip (SoCs), licensed its Parser Platform to function as the front end to Qualib, library quality inspection software.

Read more at EDACafe.com.