Verific Design Automation today confirmed its Parser Platform serves as the front end to Symbiotic EDA’s system-on-chip (SoC) synthesis, formal verification and field programmable gate array (FPGA) chip design software.
Celebrating 20 Years of Exceptional Support, Part 6
The six-part series of interviews with some of Verific’s biggest user fans concludes with profiles of Wolfgang Roesner, IBM Fellow for Hardware Verification and Verification Tools, and serial entrepreneur George Janac.
Celebrating 20 Years of Exceptional Support, Part 5
Going the Extra Mile
ANSYS Semiconductor’s Vic Kulkarni, who serves as its vice president and chief strategist, offers a fitting tribute to Verific. “Verific goes the extra mile and provides solutions head and shoulders above others.”
Celebrating 20 Years of Exceptional Support, Part 4
Good Partnership on All Levels
A profile of Verific’s partnership with Real Intent is the next post in the series. Rajiv Kumar, its vice president of engineering, details the relationship between the two companies. As far as he’s concerned, there’s no need to look at another vendor.
Celebrating 20 Years of Exceptional Support, Part 3
The Silent Partner
The blog post series resumes with Andrew Dauman, vice president of engineering at Tortuga Logic, who considers Verific to be a silent partner. Verific’s impact on the industry has never been visible, but it’s significant, nonetheless.
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