I had an interesting conversation with Michiel Ligthart and Rick Carlson of Verific. They have a unique niche in the EDA ecosystem. They provide parsers for SystemVerilog, VHDL, and IEEE 1801 (fka UPF). They really have no competition other than companies that develop their own parsers in-house, usually for historical reasons.
Michiel Ligthart, President and COO of Verific Design Automation, and Rick Carlson, VP of Worldwide Sales, have a proposal for young companies in the EDA industry and adjacent technologies: Come to Verific if your organization is early stage, in need of encouragement and wise counsel, and could benefit from access to Verific software to help you progress towards a commercial product launch.
Read more at edacafe.com
Robert Gardner, longtime member of the Verific Design Automation Board of Directors, will be presented with the yearly DATE Fellow Award by the Design, Automation and Test in Europe (DATE) Conference and Exhibit 2016.
He will receive the prestigious award in recognition of his long association and support of DATE during the Opening Ceremonies March 15.
Read more at finance.yahooc.om
Invionics, a company providing software to accelerate integrated circuit (IC) development and design automation, today took the wraps off the VRDM Development Platform that layers a rapid development interface on top of Verific’s industry-standard, IEEE-compliant SystemVerilog and VHDL parsers.