Invionics, a company providing software to accelerate integrated circuit (IC) development and design automation, today took the wraps off the VRDM Development Platform that layers a rapid development interface on top of Verific’s industry-standard, IEEE-compliant SystemVerilog and VHDL parsers.
“We’re delighted that So-ADE founders created a product around our parser platform, and they have our full support,” notes Michiel Ligthart, Verific’s president and chief operating officer.
Today’s announcement reinforces Verific’s reach into a wide variety of verification segments, including analysis, emulation, simulation and synthesis.
Verific Design Automation, provider of SystemVerilog, VHDL and UPF parsers, today announced Rocketick Technologies Ltd., a leading provider of Verilog simulation acceleration solutions for chip verification, has renewed its license for Verific’s SystemVerilog Parser Platform.
“Verific has been an outstanding partner,” adds Uri Tal, Rocketick’s chief executive officer. “Its software is high quality, as is the support and service. I can’t think of a more responsive and supportive EDA vendor.”
Rob Dekker’s involvement in logic synthesis technology spans more than 20 years. He’s developed a thriving business selling register-transfer-level (RTL) parsers and elaborators to companies offering commercial EDA tools and electronics companies implementing or upgrading their design flows. I spoke with him about trends in the electronics area. Read more at electronicdesign.com
Verific Design Automation specializes in Verilog, VHDL and SystemVerilog language processing sub-systems. Its users develop software where Verific-based technology serves as the front end for a wide range of EDA and FPGA design tools. These tools are used during analysis, simulation, verification, synthesis, emulation and test.
This article discusses the use of Verific technology by our team at the Really Useful Software and Hardware Company. We hope these experiences will be of use to the many other Verific users out there and we also describe our own efforts to extend the technology with a series of ‘apps’ addressing common tool developer issues.
Verific Design Automation today announced Flexras Technologies, provider of high-performance partitioning software, has implemented its industry-standard, IEEE-compliant SystemVerilog and VHDL parsers as the front end to the Wasga™ Compiler Design Suite for field programmable gate array (FPGA)-based prototyping.
Electronic Design Automation (EDA) component software leaders Concept Engineering and Verific Design Automation today announced immediate availability of a connectivity package that links Concept Engineering’s NlviewTM schematic generator and visualization engine with Verific’s netlist database.
Verific Design Automation, supplier of industry-standard, IEEE-compliant SystemVerilog and VHDL parsers, today announced enhancements to its parser forthe IEEE 1801-2013standard for the design and verification of low-power integrated circuits, also known as Universal Power Format 2.1 (UPF 2.1).