News - Verific Design Automation

28 February 2017

Focus on core competency, outsource the rest

A startup can shave 12 months or more off the development cycle by outsourcing non-essential elements of product design.

I’m hearing from different sources that investments in electronic design automation (EDA) and semiconductor startups are picking up around the globe and not just in Silicon Valley. That’s welcome news –– and long overdue –– as we move through 2017. With funding come new and innovative products and the cycle of growth to acquisition or other successful outcomes endures.

Verific: the Name is Short for Verification…

I had an interesting conversation with Michiel Ligthart and Rick Carlson of Verific. They have a unique niche in the EDA ecosystem. They provide parsers for SystemVerilog, VHDL, and IEEE 1801 (fka UPF). They really have no competition other than companies that develop their own parsers in-house, usually for historical reasons.

Verific Rhymes With Terrific

Michiel Ligthart, President and COO of Verific Design Automation, and Rick Carlson, VP of Worldwide Sales, have a proposal for young companies in the EDA industry and adjacent technologies: Come to Verific if your organization is early stage, in need of encouragement and wise counsel, and could benefit from access to Verific software to help you progress towards a commercial product launch.
Read more at edacafe.com

24 May 2016

Cutting-edge EDA Startups rely on Verific

Verific to Showcase Three Design Automation Startups With Safety-Features Insertion, Low-Power, Hardware Security Analysis Offerings in Its DAC Booth
Read more at finance.yahoo.com

19 April 2016

Verific licensee S2C upgrades to SystemVerilog

Verific Design Automation, the recognized leader of SystemVerilog, VHDL and UPF parsers used throughout the semiconductor industry, announced today S2C, Inc., a leading provider of FPGA-based rapid prototyping solutions, licensed its SystemVerilog parser. Read more at finance.yahoo.com

9 March 2016

Verific’s board member Bob Gardner honored with DATE fellow award

Robert Gardner, longtime member of the Verific Design Automation Board of Directors, will be presented with the yearly DATE Fellow Award by the Design, Automation and Test in Europe (DATE) Conference and Exhibit 2016.

He will receive the prestigious award in recognition of his long association and support of DATE during the Opening Ceremonies March 15.
Read more at finance.yahooc.om

14 January 2016

UPF 3.0 is Now Official

The new UPF 3.0 standard offers additional enhancements to address and describe power intent of complex systems on chip (SoCs).
Read more at eetimes.com

20 October 2015

Verific Design Integrated with Tortuga Logic’s Hardware Security Tools

Tortuga Logic, transforming the way hardware designers and system architects test the security of hardware design, has licensed the Parser Platform from Verific Design Automation, the recognized leader of SystemVerilog, VHDL and UPF parsers used throughout the semiconductor industry.
Read more

14 July 2015

Vtool Relies on Verific Parsers to Drive Disruptive, Functional Verification Platform

Verific Design Automation, recognized as the leading supplier of hardware description language (HDL) parsers used throughout the semiconductor industry, today announced electronic design automation (EDA) newcomer Vtool has chosen Verific’s parsers for use with its functional verification platform.
Read more

15 May 2015

Invionics Unveils VRDM for Rapid Deployment of Verific’s Parsers

Invionics, a company providing software to accelerate integrated circuit (IC) development and design automation, today took the wraps off the VRDM Development Platform that layers a rapid development interface on top of Verific’s industry-standard, IEEE-compliant SystemVerilog and VHDL parsers.