News - Verific Design Automation

3 December 2019

vSync Circuits Adds Verific’s Static Elaborator to Product Mix

Verific Design Automation today announced long-time customer vSync Circuits added Verific’s static elaboration to its product mix and introduced vLinter, early rule-based design analysis and verification software.

29 May 2019

Verific, 20 Years Terrific

What do JasperGold, Stratus, and the Rocketick part of Xcelium have in common? Well, they are all Cadence products, of course. But they also all use Verific as parsers for SystemVerilog, Verilog, and VHDL.

Verific got started twenty years ago, Rob Dekker told me.

26 April 2019

Foundational Excellence in a Laid-Back Style

I recently had a call with Rob Dekker, Founder and CTO of Verific. If you’re in EDA or semiconductor CAD, chances are high that you know who they are. They’re king of the hill in parser software for SystemVerilog and VHDL.

Verific celebrates 20 years

Sanjay Gangal interviewed Michiel Ligthart, President and COO at Verific Design Automation at the 2019 DVCon.

Watch the video at EDAcafe.com.

12 October 2018

Innergy Systems Powers Up with Verific

Verific Design Automation today announced Innergy Systems licensed its Parser Platform to serve as the front end to its new Power Analysis Platform that combines quick-debug power analysis with fast power model generation.

Verific’s Parser Platform License Secured by Empyrean

Verific Design Automation today announced Empyrean, provider of fast and physically aware, design closure and optimization solutions for systems on chip (SoCs), licensed its Parser Platform to function as the front end to Qualib, library quality inspection software.

Verific Integrates INVIO with Flagship Parsers

Verific today announced full integration of INVIO with its flagship parser platforms. This follows an earlier announcement that it acquired from Invionics Software the INVIO platform, with its high-level level application programming interfaces (APIs) that enable Verific users to simplify and streamline their design environment, accelerating tool development.

Verific’s Parser Platform Selected by Efinix

Verific Design Automation today announced Efinix™, an innovator in programmable product platforms and technology, selected its Verilog Parser Platform and register transfer level (RTL) elaborator to serve as the front end to the Efinity™ Integrated Design Environment (IDE).

Baum Licenses Verific’s Parser Platform

Baum, a leader in power analysis solutions, today became the newest licensee of Verific Design Automation, the recognized leader of SystemVerilog, VHDL and UPF Parser Platforms in production and development use throughout the semiconductor industry.

Verific Acquires INVIO Platform

Under terms of the agreement, Verific will acquire Invionics Software’s entire INVIO technology portfolio, for electronic design automation (EDA) tools and flows. An R&D group with real-world design experience and a deep understanding of EDA software development will join Verific’s engineering department.