Verific Design Automation, provider of SystemVerilog, VHDL and UPF parsers, finished its fifth consecutive year of growth with a double-digit increase in revenue.
Read more at finance.yahoo.com
Q&A with Verific’s Rob Dekker on Parsers, Elaborators
Rob Dekker’s involvement in logic synthesis technology spans more than 20 years. He’s developed a thriving business selling register-transfer-level (RTL) parsers and elaborators to companies offering commercial EDA tools and electronics companies implementing or upgrading their design flows. I spoke with him about trends in the electronics area. Read more at electronicdesign.com
Exploiting Verific tools at the right abstraction level
Verific Design Automation specializes in Verilog, VHDL and SystemVerilog language processing sub-systems. Its users develop software where Verific-based technology serves as the front end for a wide range of EDA and FPGA design tools. These tools are used during analysis, simulation, verification, synthesis, emulation and test.
This article discusses the use of Verific technology by our team at the Really Useful Software and Hardware Company. We hope these experiences will be of use to the many other Verific users out there and we also describe our own efforts to extend the technology with a series of ‘apps’ addressing common tool developer issues.
Flexras adds Verific’s VHDL and SystemVerilog parsers
Verific Design Automation today announced Flexras Technologies, provider of high-performance partitioning software, has implemented its industry-standard, IEEE-compliant SystemVerilog and VHDL parsers as the front end to the Wasga™ Compiler Design Suite for field programmable gate array (FPGA)-based prototyping.
Read more
Menta follows FPGA leaders by selecting Verific
Connectivity package links Concept’s schematics and Verific’s parsers
Electronic Design Automation (EDA) component software leaders Concept Engineering and Verific Design Automation today announced immediate availability of a connectivity package that links Concept Engineering’s NlviewTM schematic generator and visualization engine with Verific’s netlist database.
Verific adds enhanced support for UPF
Verific Design Automation, supplier of industry-standard, IEEE-compliant SystemVerilog and VHDL parsers, today announced enhancements to its parser forthe IEEE 1801-2013standard for the design and verification of low-power integrated circuits, also known as Universal Power Format 2.1 (UPF 2.1).
Verific increases revenue by 15%
Verific Design Automation, provider of SystemVerilog, Verilog and VHDL parsers, closed 2013 with a double-digit increase in revenue and56 active user companies, many of whom are longstanding customers.
Tabula upgrades to SystemVerilog
Verific Design Automation, provider of SystemVerilog, Verilog and VHDL parsers, today announced that Tabula (www.tabula.com) has added Verific’s SystemVerilog parser as front-end support to version 2.7.1 of its Stylus® compiler.
Verific increases revenue by 20%
Verific Design Automation, provider of SystemVerilog, Verilog and VHDL parsers, ended 2012 with 52 active user companies and a revenue increase of 20% over 2011.