Verific Design Automation’s Verilog Test Suites cover syntax and semantics of Verilog 2001, Verilog-AMS, and SystemVerilog.
Other than conventional LRM tests, Verific’s tests concentrate on the synthesizable subset of Verilog, thus providing superior coverage for EDA products.
The test suite covers SystemVerilog IEEE 1800, Verilog-AMS 2.0 (approved by Open Verilog International, 2000), IEEE-1364 and Verilog-2001.
All test cases are arranged according to the section number as provided in the LRM. Also each test case clearly states the feature that is being tested. All related test cases are grouped together under the same category. Inside a group every test case is stored under a separate directory. Each synthesizable test case has a bench file.
Designs which are not synthesizable are self testing. A large set of miscellaneous designs combines different SystemVerilog features and also features of Verilog-95/Verilog-2001.
Finally, the test suites include a rich set of negative test cases.
Our test suites are industry proven and in use with several leading EDA companies. We currently have the following suites available:
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