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Archives for May 2017

23 May 2017

Verific signs functional safety provider Austemper

SystemVerilog and VHDL parsers from Verific serve as the front end to Austemper’s software that analyzes, augments and verifies functional safety in system-on-chip (SoC), application specific integrated circuit (ASIC) and intellectual property (IP) designs ensuring they meet functional safety requirements.

Read more at MarketWired.

Filed Under: Geen categorie

19 May 2017

Verific Adds UPF Elaborator to Comprehensive Parser Platform Portfolio

New Functionality Broadens UPF Parser/Analyzer Capabilities

Verific Design Automation, the recognized leader of SystemVerilog, VHDL and Unified Power Format (UPF) Parser Platforms in production and development use throughout the semiconductor industry, today announced availability of its UPF Elaborator.

Read more at MarketWired.

Filed Under: Geen categorie

Design Automation Conference

Rick Carlson at DAC 2017
Interview with Rick Carlson, VP of Sales, at DAC 2018

DAC interview video
Interview with Rob Dekker at DAC 2016

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