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Archives for May 2011

20 May 2011

Verific unveils Perl interface for its SystemVerilog and VHDL front-end solutions

The folks at Verific Design Automation, long known for their SystemVerilog and VHDL front-end solutions used by leading EDA, FPGA and semiconductor companies worldwide, have just unveiled a Perl interface to their industry-standard, IEEE-compliant SystemVerilog and VHDL parsers and elaborators.

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