Verific Design Automation, supplier of industry-standard, IEEE-compliant SystemVerilog and VHDL front-end solutions, has been selected by Blue Pearl Software to support its Blue Pearl Software Suite.
Archives for February 2012
Verific adds UPF 2.0 to Parser Platform
Verific Design Automation today announced immediate availability of a parser for the IEEE 1801-2009 Standard for Design and Verification of Low-Power Integrated Circuits. Also known as Unified Power Format 2.0 (UPF 2.0), it was developed by standards organization Accellera and carries the support of multiple EDA vendors.