User contributions
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- 15:18, 28 February 2019 (diff | hist) . . (+1) . . Prettyprint to a string
- 15:17, 28 February 2019 (diff | hist) . . (+64) . . Prettyprint to a string
- 13:11, 28 February 2019 (diff | hist) . . (-8) . . Prettyprint to a string
- 13:10, 28 February 2019 (diff | hist) . . (+5) . . Main Page
- 13:09, 28 February 2019 (diff | hist) . . (+145) . . Prettyprint to a string
- 13:07, 28 February 2019 (diff | hist) . . (0) . . Prettyprint to a string
- 10:46, 27 February 2019 (diff | hist) . . (+258) . . Tcl library path
- 15:48, 21 February 2019 (diff | hist) . . (+15) . . Main Page
- 15:48, 21 February 2019 (diff | hist) . . (-6) . . What languages can I use with Verific software? (current)
- 14:30, 15 February 2019 (diff | hist) . . (+964) . . N Cross-reference between the original RTL files and the elaborated netlist (Created page with "'''Q: Is there a cross-reference between the original RTL design files and the elaborated netlist? We need this for our application. If any issue found in the elaborated netli...") (current)
- 14:19, 15 February 2019 (diff | hist) . . (+197) . . Main Page
- 10:52, 12 February 2019 (diff | hist) . . (+11) . . Design with System Verilog and Verilog 2001 files (current)
- 10:47, 12 February 2019 (diff | hist) . . (+19) . . m Main Page
- 16:41, 28 December 2018 (diff | hist) . . (+1,087) . . Top level module with interface ports (current)
- 16:27, 28 December 2018 (diff | hist) . . (+1,706) . . N Defined macros become undefined - MFCU vs SFCU (Created page with "'''Q: I have macros defined in a separate input file. Why does Verific analyzer complain about "undefined macros" in SystemVerilog mode but not in Verilog 2K mode?''' SystemV...")
- 16:13, 28 December 2018 (diff | hist) . . (+1) . . Main Page
- 16:12, 28 December 2018 (diff | hist) . . (+157) . . Main Page
- 16:04, 28 December 2018 (diff | hist) . . (+24) . . Main Page
- 15:19, 28 December 2018 (diff | hist) . . (+851) . . N Top level module with interface ports (Created page with "'''Q: How to elaborate top-level module with interface ports.''' When I elaborate a top-level module with interface ports, Verific issues a warning message and stops the elab...")
- 13:07, 28 December 2018 (diff | hist) . . (+120) . . Main Page
- 09:30, 26 November 2018 (diff | hist) . . (-773) . . Talk:Main Page (Blanked the page) (current)
- 11:26, 11 September 2018 (diff | hist) . . (+119) . . Does Verific support XMR?
- 10:58, 31 August 2018 (diff | hist) . . (+54) . . Support IEEE 1735 encryption standard
- 17:03, 30 August 2018 (diff | hist) . . (+678) . . N Support IEEE 1735 encryption standard (Created page with "'''Q:Does Verific provide support for IEEE 1735 encryption standard?''' Verific does not implement the decryption/encryption algorithms. This task is appropriately reserved t...")
- 17:00, 30 August 2018 (diff | hist) . . (+111) . . Main Page
- 16:11, 24 August 2018 (diff | hist) . . (+20) . . How to get type/initial value of parameters
- 16:10, 24 August 2018 (diff | hist) . . (+3) . . How to ignore parameters/generics in elaboration
- 16:10, 24 August 2018 (diff | hist) . . (+11) . . How to create a Netlist database from scratch (not from RTL input) (current)
- 16:09, 24 August 2018 (diff | hist) . . (+20) . . How to ignore parameters/generics in elaboration
- 16:01, 24 August 2018 (diff | hist) . . (+3,381) . . N How to create a Netlist database from scratch (not from RTL input) (Created page with "A Perl example: <nowiki> #!/usr/bin/perl use strict; push (@INC,"../../../extra_tests/pm"); require "Verific.pm"; # The global Libset is already at the top of the netlist...")
- 16:00, 24 August 2018 (diff | hist) . . (+142) . . Main Page
- 15:58, 24 August 2018 (diff | hist) . . (+31) . . Main Page
- 15:39, 24 August 2018 (diff | hist) . . (+299) . . Message handling
- 14:37, 24 August 2018 (diff | hist) . . (+865) . . N How to check for errors in analysis/elaboration (Created page with "'''Q:Verific clears the error count at various steps during analysis/elaboration. Is there a way to tell if these processes have errors?''' Verific follows an "optimistic" ap...")
- 14:29, 24 August 2018 (diff | hist) . . (+141) . . Main Page
- 11:42, 24 August 2018 (diff | hist) . . (+526) . . Constant expression replacement
- 11:31, 24 August 2018 (diff | hist) . . (+1,527) . . N How to ignore parameters/generics in elaboration (Created page with "'''Q:Is there a way to tell the elaborator to ignore certain parameters/generics so that the unit/module is not uniquified?''' Specific parameters/generics of specific module...")
- 11:23, 24 August 2018 (diff | hist) . . (+190) . . Main Page
- 11:14, 3 July 2017 (diff | hist) . . (+631) . . N Release version (Created page with "'''Q: How do I tell the version of a Verific software release? ''' The APIs: Message::ReleaseString() Message::ReleaseDate() respectively return the release string (e.g...")
- 11:05, 3 July 2017 (diff | hist) . . (+82) . . Main Page
- 14:02, 26 June 2017 (diff | hist) . . (+992) . . N Tcl library path (Created page with "'''Q: When trying to build, I get the error message: "/usr/bin/ld: cannot find -ltcl". How do I correct that problem?''' First, verify that you have tcl and tcl dev installed...")
- 13:49, 26 June 2017 (diff | hist) . . (+97) . . Main Page
- 15:36, 14 June 2017 (diff | hist) . . (-15) . . How to get type/initial value of parameters
- 12:35, 14 June 2017 (diff | hist) . . (+19) . . Does Verific support XMR?
- 12:34, 14 June 2017 (diff | hist) . . (+1) . . Does Verific support XMR?
- 09:36, 14 June 2017 (diff | hist) . . (+561) . . N How to get enums from Verilog parsetree (Created page with "'''Q: From the parsetree, how can I get the enums declared in a module?''' You can use the following code snippet: VeriModule *mod = ... ; VeriScope *scope = mod->GetSco...") (current)
- 09:32, 14 June 2017 (diff | hist) . . (+123) . . Main Page
- 15:47, 11 May 2017 (diff | hist) . . (+696) . . N How to identify packages being imported into a module (Created page with "'''Q: How do I identify packages being imported into a module?''' Code example: MapIter mi ; VeriModule *mod ; FOREACH_VERILOG_MODULE(mi, mod) { if (!mod || !mod->...") (current)
- 15:46, 11 May 2017 (diff | hist) . . (0) . . Main Page
- 15:46, 11 May 2017 (diff | hist) . . (+129) . . m Main Page
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