User contributions
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- 13:44, 3 September 2025 (diff | hist) . . (+115) . . How to evaluate a Verilog expression
- 13:39, 3 September 2025 (diff | hist) . . (+44) . . How to evaluate a Verilog expression
- 13:38, 3 September 2025 (diff | hist) . . (+4,305) . . How to evaluate a Verilog expression
- 11:18, 3 September 2025 (diff | hist) . . (+64) . . How to evaluate a Verilog expression
- 11:17, 3 September 2025 (diff | hist) . . (+1) . . How to evaluate a Verilog expression
- 11:15, 3 September 2025 (diff | hist) . . (-22) . . How to evaluate a Verilog expression
- 10:46, 3 September 2025 (diff | hist) . . (+98) . . How to evaluate a Verilog expression
- 10:44, 3 September 2025 (diff | hist) . . (-1) . . How to evaluate a Verilog expression
- 14:36, 2 September 2025 (diff | hist) . . (+55) . . How to evaluate a VHDL expression (current)
- 14:33, 2 September 2025 (diff | hist) . . (-1) . . How to evaluate a VHDL expression
- 14:32, 2 September 2025 (diff | hist) . . (+3,924) . . How to evaluate a VHDL expression
- 14:13, 2 September 2025 (diff | hist) . . (+6,816) . . N How to evaluate a VHDL expression (Created page with "'''>>> This page is under construction <<<''' Unlike in Verilog, expression evaluation in VHDL is fairly involved and needs all of the following: * Either static elaborated...")
- 14:00, 2 September 2025 (diff | hist) . . (+86) . . Main Page
- 08:53, 12 August 2025 (diff | hist) . . (-86) . . Getting design hierarchy from input RTL files (current)
- 14:11, 22 July 2025 (diff | hist) . . (-1) . . Source code customization & Stable release services (current)
- 14:09, 22 July 2025 (diff | hist) . . (0) . . Source code customization & Stable release services
- 11:12, 14 July 2025 (diff | hist) . . (+9,476) . . N Getting design hierarchy from input RTL files (Created page with "C++ application: <nowiki> #include <sstream> #include <iostream> #include <fstream> #include <string> #include "Array.h" // Make class Array available #include "Set....")
- 10:52, 14 July 2025 (diff | hist) . . (+120) . . Main Page
- 16:21, 30 June 2025 (diff | hist) . . (-150) . . Pretty-print a module and the packages imported by the module (current)
- 09:53, 23 April 2025 (diff | hist) . . (-248) . . Notes on analysis (current)
- 09:11, 6 March 2025 (diff | hist) . . (+88) . . LineFile data from input files (current)
- 09:06, 21 February 2025 (diff | hist) . . (+241) . . How to evaluate a Verilog expression
- 09:20, 20 February 2025 (diff | hist) . . (+2,888) . . N How to evaluate a Verilog expression (Created page with "This applicatione example shows how to evaluate a Verilog expression. Note that it requires 'Static Elaboration' feature. C++: <nowiki> #include "veri_file.h" #include "Veri...")
- 09:15, 20 February 2025 (diff | hist) . . (+95) . . Main Page
- 17:41, 18 October 2024 (diff | hist) . . (+88) . . Modules with ' 1' ' 2' suffix in their names (current)
- 17:15, 18 October 2024 (diff | hist) . . (+69) . . Remove Verific data structures (current)
- 17:11, 18 October 2024 (diff | hist) . . (+40) . . Modules/design units with " default" suffix in their names (current)
- 17:10, 18 October 2024 (diff | hist) . . (+82) . . Modules with ' 1' ' 2' suffix in their names
- 17:08, 18 October 2024 (diff | hist) . . (+7) . . Main Page
- 17:06, 18 October 2024 (diff | hist) . . (+2,240) . . Modules/design units with " default" suffix in their names
- 15:04, 6 September 2024 (diff | hist) . . (+403) . . Simple example of visitor pattern (current)
- 21:27, 24 July 2024 (diff | hist) . . (+1,268) . . Support IEEE 1735 encryption standard
- 09:10, 18 June 2024 (diff | hist) . . (+538) . . How to parse a string (current)
- 09:23, 8 May 2024 (diff | hist) . . (+186) . . Source code customization & Stable release services
- 10:35, 23 April 2024 (diff | hist) . . (+3,785) . . N Using TypeRange table to retrieve the originating type-range for an id (Created page with "C++: <nowiki> #include "veri_file.h" #include "DataBase.h" #include "Map.h" #include "Set.h" #ifdef VERIFIC_NAMESPACE using namespace Verific ; #endif int main() { Runt...") (current)
- 10:30, 23 April 2024 (diff | hist) . . (+190) . . Main Page
- 18:52, 3 April 2024 (diff | hist) . . (+52) . . In Verilog parsetree adding names to unnamed instances (current)
- 16:05, 28 February 2024 (diff | hist) . . (+114) . . SystemVerilog "std" package (current)
- 16:41, 25 January 2024 (diff | hist) . . (-6) . . Instance - Module binding order (current)
- 08:51, 17 November 2023 (diff | hist) . . (-1) . . Constant expression replacement (current)
- 20:53, 31 October 2023 (diff | hist) . . (-5) . . Notes on analysis
- 20:52, 31 October 2023 (diff | hist) . . (+136) . . Notes on analysis
- 11:13, 20 October 2023 (diff | hist) . . (0) . . Notes on analysis
- 08:32, 20 October 2023 (diff | hist) . . (+126) . . Notes on analysis
- 16:25, 11 October 2023 (diff | hist) . . (+268) . . How to get best support from Verific (current)
- 13:15, 10 October 2023 (diff | hist) . . (-8) . . How to change name of id in Verilog parsetree (current)
- 09:59, 29 September 2023 (diff | hist) . . (-86) . . Traverse instances in parsetree
- 09:57, 29 September 2023 (diff | hist) . . (+367) . . Traverse instances in parsetree
- 12:19, 22 August 2023 (diff | hist) . . (+3,244) . . N Finding hierarchical paths of a Netlist (Created page with "This application displays all hierarchical paths of Netlist of Cell 'bot1' in the Netlist Database. <nowiki> #include "veri_file.h" #include "DataBase.h" #include "Strings.h...") (current)
- 12:12, 22 August 2023 (diff | hist) . . (+102) . . Main Page
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