User contributions
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- 17:16, 12 May 2022 (diff | hist) . . (+2,489) . . N Simple examples of VHDL visitor pattern (Created page with " <nowiki> [hoa@awing0 220512b]$ cat test.cpp #include "vhdl_file.h" #include "VhdlUnits.h" #include "VhdlIdDef.h" #include "VhdlValue_Elab.h" #include "Strings.h" #ifdef VERI...")
- 17:14, 12 May 2022 (diff | hist) . . (+11) . . Main Page
- 17:13, 12 May 2022 (diff | hist) . . (+87) . . Main Page
- 14:22, 3 May 2022 (diff | hist) . . (+30) . . Access attributes in parsetree (current)
- 09:26, 14 April 2022 (diff | hist) . . (+3,558) . . N How to ignore certain modules while analyzing input RTL files (Created page with "The code example below shows how to ignore certain modules in the input RTL files. The ignored modules will not be present in the parsetree. C++ code: <nowiki> #include "Arr...") (current)
- 08:49, 14 April 2022 (diff | hist) . . (+145) . . Main Page
- 15:45, 4 March 2022 (diff | hist) . . (0) . . Black box, empty box, and unknown box (current)
- 15:44, 4 March 2022 (diff | hist) . . (+75) . . Black box, empty box, and unknown box
- 20:05, 10 February 2022 (diff | hist) . . (-66) . . How to save computer resources
- 21:09, 26 January 2022 (diff | hist) . . (-1) . . How to parse a string (current)
- 21:08, 26 January 2022 (diff | hist) . . (-15) . . How to parse a string
- 11:38, 26 January 2022 (diff | hist) . . (+31) . . Notes on analysis
- 12:56, 29 December 2021 (diff | hist) . . (+383) . . Static elaboration
- 21:30, 3 December 2021 (diff | hist) . . (+150) . . System attributes
- 21:26, 3 December 2021 (diff | hist) . . (+135) . . System attributes
- 18:57, 1 December 2021 (diff | hist) . . (+90) . . Black box, empty box, and unknown box
- 17:52, 3 November 2021 (diff | hist) . . (+8) . . Black box, empty box, and unknown box
- 12:38, 27 October 2021 (diff | hist) . . (-21) . . Statically elaborate with different values of parameters (current)
- 12:38, 27 October 2021 (diff | hist) . . (-21) . . Simple example of visitor pattern
- 14:45, 26 October 2021 (diff | hist) . . (+133) . . How to traverse scope hierarchy (current)
- 16:12, 20 October 2021 (diff | hist) . . (-1) . . How to parse a string
- 10:34, 15 October 2021 (diff | hist) . . (-10) . . Main Page
- 10:32, 15 October 2021 (diff | hist) . . (-54) . . How to get best support from Verific
- 09:21, 15 October 2021 (diff | hist) . . (-1) . . Notes on analysis
- 08:52, 15 October 2021 (diff | hist) . . (-1) . . Notes on analysis
- 08:52, 15 October 2021 (diff | hist) . . (+2) . . Notes on analysis
- 08:51, 15 October 2021 (diff | hist) . . (+152) . . Notes on analysis
- 17:49, 14 October 2021 (diff | hist) . . (+1) . . Notes on analysis
- 15:55, 12 October 2021 (diff | hist) . . (+66) . . How to save computer resources
- 11:32, 8 October 2021 (diff | hist) . . (-28) . . Main Page
- 11:31, 8 October 2021 (diff | hist) . . (+108) . . Escaped identifiers in RTL files and in Verific data structures
- 11:13, 8 October 2021 (diff | hist) . . (-33) . . System attributes
- 11:12, 8 October 2021 (diff | hist) . . (+315) . . System attributes
- 20:08, 4 October 2021 (diff | hist) . . (-174) . . Source code customization & Stable release services
- 20:07, 4 October 2021 (diff | hist) . . (+28) . . Source code customization & Stable release services
- 20:06, 4 October 2021 (diff | hist) . . (+3) . . Source code customization & Stable release services
- 19:53, 4 October 2021 (diff | hist) . . (+1) . . Source code customization & Stable release services
- 19:53, 4 October 2021 (diff | hist) . . (+3) . . Source code customization & Stable release services
- 10:07, 30 September 2021 (diff | hist) . . (+3) . . m Source code customization & Stable release services
- 10:00, 30 September 2021 (diff | hist) . . (+206) . . Source code customization & Stable release services
- 09:57, 30 September 2021 (diff | hist) . . (-15) . . Source code customization & Stable release services
- 09:56, 30 September 2021 (diff | hist) . . (+1,763) . . Source code customization & Stable release services
- 09:49, 30 September 2021 (diff | hist) . . (+314) . . N Source code customization & Stable release services (Created page with ">>> Under construction <<< Verific offers two services to licensees: Source Code Customization and Stable Release. On Verific's file system, each of the licensees has a sepa...")
- 09:46, 30 September 2021 (diff | hist) . . (+122) . . Main Page
- 13:59, 28 September 2021 (diff | hist) . . (+3) . . Black box, empty box, and unknown box
- 17:23, 31 August 2021 (diff | hist) . . (+583) . . LineFile data from input files (current)
- 11:39, 9 August 2021 (diff | hist) . . (-1) . . How to get packed dimensions of enum
- 11:39, 9 August 2021 (diff | hist) . . (+714) . . How to get packed dimensions of enum
- 10:24, 6 August 2021 (diff | hist) . . (-265) . . LineFile data from input files
- 09:18, 6 August 2021 (diff | hist) . . (+265) . . LineFile data from input files
- 13:14, 27 July 2021 (diff | hist) . . (+41) . . Accessing and evaluating module's parameters (current)
- 12:44, 27 July 2021 (diff | hist) . . (-4) . . Accessing and evaluating module's parameters
- 12:43, 27 July 2021 (diff | hist) . . (+11) . . Accessing and evaluating module's parameters
- 12:40, 27 July 2021 (diff | hist) . . (+4,589) . . N Accessing and evaluating module's parameters (Created page with " <nowiki> #include "Map.h" #include "Array.h" #include "Strings.h" #include "veri_file.h" #include "VeriBaseValue_Stat.h" #include "VeriModule.h" #include "VeriExpression.h" #...")
- 12:36, 27 July 2021 (diff | hist) . . (+111) . . Main Page
- 12:03, 9 July 2021 (diff | hist) . . (+13) . . Notes on analysis
- 12:03, 9 July 2021 (diff | hist) . . (-3) . . Notes on analysis
- 11:58, 9 July 2021 (diff | hist) . . (-1) . . Notes on analysis
- 10:36, 9 July 2021 (diff | hist) . . (+36) . . Notes on analysis
- 10:31, 9 July 2021 (diff | hist) . . (+39) . . Notes on analysis
- 09:59, 9 July 2021 (diff | hist) . . (+791) . . N Notes on analysis (Created page with "This is a place holder for notes regarding analysis of System Verilog designs. Can I use veri_file::Analyze to read SV input files one by one? Yes. But if you have multiple...")
- 09:52, 9 July 2021 (diff | hist) . . (+59) . . Main Page
- 11:18, 25 June 2021 (diff | hist) . . (+4) . . How to get best support from Verific
- 11:10, 25 June 2021 (diff | hist) . . (+103) . . How to get best support from Verific
- 15:07, 23 June 2021 (diff | hist) . . (+63) . . Remove Verific data structures (current)
- 13:02, 17 June 2021 (diff | hist) . . (+8) . . How to parse a string
- 12:46, 17 June 2021 (diff | hist) . . (+46) . . Main Page
- 12:45, 17 June 2021 (diff | hist) . . (+3) . . How to parse a string
- 12:44, 17 June 2021 (diff | hist) . . (+1,910) . . How to parse a string
- 10:33, 11 June 2021 (diff | hist) . . (-18) . . Defined macros become undefined - MFCU vs SFCU (current)
- 10:33, 11 June 2021 (diff | hist) . . (-51) . . Defined macros become undefined - MFCU vs SFCU
- 10:27, 11 June 2021 (diff | hist) . . (-20) . . How to detect multiple-clock-edge condition in Verilog parsetree (current)
- 10:26, 11 June 2021 (diff | hist) . . (+448) . . How to detect multiple-clock-edge condition in Verilog parsetree
- 10:56, 9 June 2021 (diff | hist) . . (+4,535) . . N How to detect multiple-clock-edge condition in Verilog parsetree (Created page with "Multiple-clock-edge condition is not support for synthesis. For example: always @(posedge clk or negedge clk) out <= in; or in SystemVerilog dialect: always @(ed...")
- 10:43, 9 June 2021 (diff | hist) . . (0) . . Main Page
- 10:41, 9 June 2021 (diff | hist) . . (+151) . . Main Page
- 13:06, 5 May 2021 (diff | hist) . . (+74) . . How to get best support from Verific
- 10:35, 3 May 2021 (diff | hist) . . (-1) . . Remove Verific data structures
- 10:33, 3 May 2021 (diff | hist) . . (-27) . . Remove Verific data structures
- 16:00, 21 April 2021 (diff | hist) . . (+1) . . How Verific elaborator handles blackboxes/unknown boxes (current)
- 11:01, 21 April 2021 (diff | hist) . . (+2,496) . . Simple example of visitor pattern
- 10:58, 21 April 2021 (diff | hist) . . (+1) . . Main Page
- 22:46, 20 April 2021 (diff | hist) . . (0) . . Does Verific support XMR? (current)
- 15:26, 20 April 2021 (diff | hist) . . (+412) . . Pretty-print a module and the packages imported by the module
- 10:08, 20 April 2021 (diff | hist) . . (+128) . . How to get best support from Verific
- 16:11, 19 April 2021 (diff | hist) . . (+1,380) . . Buffering signals and ungrouping (current)
- 16:07, 19 April 2021 (diff | hist) . . (+7,446) . . N Buffering signals and ungrouping (Created page with "During ungrouping (flattening) a hierarchical design, there are nets that need to be merged. The name of the resulting net from the merge will be the name in the highest level...")
- 16:00, 19 April 2021 (diff | hist) . . (+129) . . Main Page
- 11:52, 19 April 2021 (diff | hist) . . (0) . . How to get library containing nested module (current)
- 11:10, 19 April 2021 (diff | hist) . . (+1) . . Main Page
- 11:08, 19 April 2021 (diff | hist) . . (+1,032) . . How to get library containing nested module
- 13:17, 12 April 2021 (diff | hist) . . (+173) . . System attributes
- 13:01, 12 April 2021 (diff | hist) . . (+112) . . System attributes
- 14:17, 8 April 2021 (diff | hist) . . (+5,308) . . N Comment out a line using text based design modification and parsetree modification (Created page with "C++: <nowiki> #include <iostream> #include "veri_file.h" #include "VeriModule.h" #include "VeriStatement.h" #include "Array.h" #include "Strings.h" #include "TextBasedDes...") (current)
- 14:16, 8 April 2021 (diff | hist) . . (0) . . Main Page
- 22:43, 30 March 2021 (diff | hist) . . (+12) . . Main Page
- 22:42, 30 March 2021 (diff | hist) . . (+9,705) . . Where in RTL does it get assigned? (current)
- 14:06, 23 March 2021 (diff | hist) . . (+6,453) . . N Where in RTL does it get assigned? (Created page with "This example illustrates how to find where a signal gets assigned in the RTL code. C++: <nowiki> #include <iostream> #include "veri_file.h" #include "VeriModule.h" #include...")
- 14:06, 23 March 2021 (diff | hist) . . (+2) . . Main Page
- 13:22, 23 March 2021 (diff | hist) . . (+6,453) . . N Where in RTL is it get assigned? (Created page with "This example illustrates how to find where a signal gets assigned in the RTL code. C++: <nowiki> #include <iostream> #include "veri_file.h" #include "VeriModule.h" #include...") (current)
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