User contributions
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- 12:50, 29 November 2016 (diff | hist) . . (+10) . . m What VeriModule* or VhdlPrimaryUnit* the Netlist comes from?
- 12:48, 29 November 2016 (diff | hist) . . (-1) . . m Main Page
- 12:47, 29 November 2016 (diff | hist) . . (+11) . . m Main Page
- 12:44, 29 November 2016 (diff | hist) . . (+9) . . m Design with VHDL-1993 and VHDL-2008 files (current)
- 12:42, 29 November 2016 (diff | hist) . . (+1) . . SystemVerilog "std" package
- 12:42, 29 November 2016 (diff | hist) . . (+6) . . Constant expression replacement
- 12:39, 29 November 2016 (diff | hist) . . (+14) . . Compile-time/run-time flags
- 12:37, 29 November 2016 (diff | hist) . . (+1) . . Design with System Verilog and Verilog 2001 files
- 12:27, 29 November 2016 (diff | hist) . . (+607) . . m Message handling
- 11:53, 29 November 2016 (diff | hist) . . (+135) . . m Remove Verific data structures
- 14:50, 23 November 2016 (diff | hist) . . (-5) . . m Remove Verific data structures
- 16:29, 22 November 2016 (diff | hist) . . (+910) . . m How to get all Verilog files being analyzed
- 15:55, 26 October 2016 (diff | hist) . . (+1,842) . . N How to get type/initial value of parameters (Created page with "'''Q: Why do I get type and initial value of parameters?''' Example Perl code: #!/usr/bin/perl # push(@INC,"../../../perlmain/install"); require "Verific.pm"; #...")
- 15:49, 26 October 2016 (diff | hist) . . (+106) . . Main Page
- 15:43, 26 October 2016 (diff | hist) . . (+90) . . Main Page
- 15:43, 26 October 2016 (diff | hist) . . (+430) . . N Prettyprint to a string (Created page with "'''Q: Why do I prettyprint a Verilog parsetree node to a string?''' Example code: VeriExpression *init_value = param_id -> GetInitialValue(); if (init_value)...")
- 11:49, 22 September 2016 (diff | hist) . . (+413) . . m Does Verific support XMR?
- 16:15, 4 August 2016 (diff | hist) . . (+5) . . m Main Page
- 16:14, 4 August 2016 (diff | hist) . . (+602) . . N Message handling (Created page with "'''Q: How do I upgrade/downgrade messages from Verific?''' For C++, use the following APIs: Message::SetMessageType() - Force a message type by message id Message::Ge...")
- 16:08, 4 August 2016 (diff | hist) . . (+71) . . m Main Page
- 16:33, 1 August 2016 (diff | hist) . . (+1) . . Constant expression replacement
- 16:32, 1 August 2016 (diff | hist) . . (+495) . . N Constant expression replacement (Created page with "'''Q: Does Verific replace constant expressions with their respective values?''' I have in my Verilog code: parameter size = 8; reg [size-1:0] foo; I expect the range...")
- 16:28, 1 August 2016 (diff | hist) . . (+121) . . m Main Page
- 11:43, 28 July 2016 (diff | hist) . . (-12) . . Remove Verific data structures
- 11:42, 28 July 2016 (diff | hist) . . (-32) . . m Remove Verific data structures
- 11:41, 28 July 2016 (diff | hist) . . (+24) . . m Remove Verific data structures
- 16:13, 27 July 2016 (diff | hist) . . (+11) . . m Main Page
- 16:12, 27 July 2016 (diff | hist) . . (+879) . . N SystemVerilog "std" package (Created page with "'''Q: Support for SystemVerilog semaphore/process/mailbox.''' When I analyzed my SystemVerilog file, Verific issued error message: test.sv(4): ERROR: process is not declare...")
- 16:05, 27 July 2016 (diff | hist) . . (+1) . . m Main Page
- 16:04, 27 July 2016 (diff | hist) . . (+97) . . m Main Page
- 16:02, 27 July 2016 (diff | hist) . . (+21) . . m Main Page
- 16:02, 27 July 2016 (diff | hist) . . (0) . . m Main Page
- 16:00, 27 July 2016 (diff | hist) . . (+65) . . m Main Page
- 15:46, 27 July 2016 (diff | hist) . . (-2) . . m Compile-time/run-time flags
- 15:40, 27 July 2016 (diff | hist) . . (+3) . . Compile-time/run-time flags
- 15:39, 27 July 2016 (diff | hist) . . (+790) . . N Compile-time/run-time flags (Created page with "'''Q: Are there options to control Verific software's behavior?''' There are compile-time flags and run-time flags to control Verific software's behavior. The compile-time f...")
- 15:29, 27 July 2016 (diff | hist) . . (+94) . . m Main Page
- 15:34, 26 July 2016 (diff | hist) . . (+1,053) . . N Included files associated with a Verilog source file (Created page with "'''Q: How do I get the list of included files associated with a Verilog source file?''' The main utility you require is: static Map *veri_file::GetIncludedFiles() ; It re...")
- 15:31, 26 July 2016 (diff | hist) . . (+140) . . m Main Page
- 15:01, 26 July 2016 (diff | hist) . . (+617) . . N Remove Verific data structures (Created page with "'''Q: How do I remove all Verific data structures in memory?''' To remove Verilog parsetree: veri_file::ResetParser(); To remove VHDL parsetree: vhdl_file::ResetPa...")
- 14:51, 26 July 2016 (diff | hist) . . (+94) . . m Main Page
- 14:15, 25 July 2016 (diff | hist) . . (+23) . . m How to get all Verilog files being analyzed
- 14:11, 25 July 2016 (diff | hist) . . (+107) . . m How to get all Verilog files being analyzed
- 19:10, 22 July 2016 (diff | hist) . . (+7) . . m Main Page
- 18:36, 22 July 2016 (diff | hist) . . (+10) . . m Main Page
- 18:34, 22 July 2016 (diff | hist) . . (+327) . . N Output file formats (Created page with "'''Q: What language formats does Verific software support as output?''' Verific software can write out: * RTL Verilog/SystemVerilog (from parsetree) * RTL VHDL (from parsetr...") (current)
- 18:30, 22 July 2016 (diff | hist) . . (0) . . m Main Page
- 18:30, 22 July 2016 (diff | hist) . . (-2) . . m Main Page
- 18:29, 22 July 2016 (diff | hist) . . (+64) . . m Main Page
- 17:54, 22 July 2016 (diff | hist) . . (+38) . . m Design with System Verilog and Verilog 2001 files
- 17:12, 22 July 2016 (diff | hist) . . (+17) . . m Does Verific support XMR?
- 17:10, 22 July 2016 (diff | hist) . . (+32) . . m Verific data structures
- 17:03, 22 July 2016 (diff | hist) . . (+24) . . m Does Verific build CDFG?
- 17:02, 22 July 2016 (diff | hist) . . (+275) . . N What languages can I use with Verific software? (Created page with "'''Q: What programming languages can I use with Verific software?''' Verific software is written in C++. But with [http://www.swig.org/ SWIG], all APIs are ported to Tcl, Pe...")
- 16:57, 22 July 2016 (diff | hist) . . (+118) . . m Main Page
- 16:56, 22 July 2016 (diff | hist) . . (-117) . . Main Page (Undo revision 211 by Hoa (talk))
- 16:54, 22 July 2016 (diff | hist) . . (+117) . . m Main Page
- 16:43, 22 July 2016 (diff | hist) . . (+8) . . m Main Page
- 16:43, 22 July 2016 (diff | hist) . . (0) . . m Verific data structures
- 16:03, 22 July 2016 (diff | hist) . . (+847) . . N How to get all Verilog files being analyzed (Created page with "'''Q: I'm using -v, -y, .... After Verific is done with the analysis, how do I get a list of all the files being analyzed?''' Use this code: Array analyzed_files ; // Array...")
- 16:03, 22 July 2016 (diff | hist) . . (+26) . . m Main Page
- 16:01, 22 July 2016 (diff | hist) . . (+672) . . N What VeriModule* or VhdlPrimaryUnit* the Netlist comes from? (Created page with "'''Q: While looking at a Netlist, is there a clean way to look back at what VeriModule* or VhdlPrimaryUnit* this netlist was derived from? ''' For example, a module: mod...")
- 16:01, 22 July 2016 (diff | hist) . . (+34) . . m Main Page
- 15:58, 22 July 2016 (diff | hist) . . (+1,602) . . N Verilog Port Expressions (Created page with "'''Q: Why are the ports in original Verilog file renamed to p1, p2, ....?''' Input file: module foo ( datain[0], datain[0] →same net into multiple port expression: ,...")
- 15:58, 22 July 2016 (diff | hist) . . (+8) . . m Main Page
- 15:57, 22 July 2016 (diff | hist) . . (-1) . . m Design with System Verilog and Verilog 2001 files
- 15:56, 22 July 2016 (diff | hist) . . (+875) . . N Design with System Verilog and Verilog 2001 files (Created page with "'''Q: For a design consisting of a mixture of Verilog 2001 and SystemVerilog input files, should I parse all the files as SystemVerilog?''' The set of SystemVerilog construc...")
- 15:56, 22 July 2016 (diff | hist) . . (+17) . . m Main Page
- 15:51, 22 July 2016 (diff | hist) . . (-84) . . m Design with VHDL-1993 and VHDL-2008 files
- 15:51, 22 July 2016 (diff | hist) . . (+739) . . N Design with VHDL-1993 and VHDL-2008 files (Created page with "'''Q: A customer wants to analyze/elaborate different VHDL flavors (1993 and 2008). They want to process the 93 files first and then the 08. As each flavor has its own IEEE li...")
- 15:50, 22 July 2016 (diff | hist) . . (-80) . . m Main Page
- 15:46, 22 July 2016 (diff | hist) . . (+9) . . m How to get module ports from Verilog parsetree (current)
- 15:45, 22 July 2016 (diff | hist) . . (+240) . . N Original RTL language (Created page with "'''Q: How do I know what language a Netlist in the netlist database comes from?''' Use attribute " language" (note the leading space): Netlist *nl; nl->GetAttValue("...")
- 15:44, 22 July 2016 (diff | hist) . . (+8) . . m Main Page
- 15:42, 22 July 2016 (diff | hist) . . (0) . . m Does Verific build CDFG?
- 15:41, 22 July 2016 (diff | hist) . . (+6) . . Does Verific build CDFG?
- 15:41, 22 July 2016 (diff | hist) . . (+65) . . m Does Verific build CDFG?
- 15:39, 22 July 2016 (diff | hist) . . (+852) . . N Does Verific support XMR? (Created page with "'''Q: Does Verific support cross module references (XMR)?''' Verific fully supports XMR with "hierarchy tree" feature. Please refer to http://www.verific.com/docs/index.php?t...")
- 15:39, 22 July 2016 (diff | hist) . . (-1) . . Main Page
- 15:37, 22 July 2016 (diff | hist) . . (+1,891) . . N Verific data structures (Created page with "'''Q: What are the data structures in Verific?''' There are 2 data structures in Verific: parsetree and netlist database. 1. The parsetree is just another representation of...")
- 15:36, 22 July 2016 (diff | hist) . . (+6) . . m Main Page
- 15:35, 22 July 2016 (diff | hist) . . (+1,891) . . N Verific data structure (Created page with "'''Q: What are the data structures in Verific?''' There are 2 data structures in Verific: parsetree and netlist database. 1. The parsetree is just another representation of...") (current)
- 14:29, 22 July 2016 (diff | hist) . . (-6) . . Main Page (Undo revision 184 by Hoa (talk))
- 14:27, 22 July 2016 (diff | hist) . . (+6) . . Main Page
- 14:26, 22 July 2016 (diff | hist) . . (+166) . . m How to get module ports from Verilog parsetree
- 14:21, 22 July 2016 (diff | hist) . . (+8) . . m How to get module ports from Verilog parsetree
- 13:07, 22 July 2016 (diff | hist) . . (+380) . . N How to get module ports from Verilog parsetree (Created page with "From the Verilog parsetree, how can I get the ports of a module? You can use the following APIs: VeriModule::GetPorts() to get the ports (Array of VeriIdDef *) from a module...")
- 13:04, 22 July 2016 (diff | hist) . . (+119) . . Main Page
- 13:01, 22 July 2016 (diff | hist) . . (+1) . . m Main Page (Undo revision 178 by Hoa (talk))
- 13:00, 22 July 2016 (diff | hist) . . (-1) . . m Main Page
- 12:58, 22 July 2016 (diff | hist) . . (+18) . . m Does Verific build CDFG?
- 12:58, 22 July 2016 (diff | hist) . . (+85) . . N Does Verific build CDFG? (Created page with "No, it does not. See [http://www.verific.com/faq/index.php?title=What_are_the_data].")
- 12:57, 22 July 2016 (diff | hist) . . (+88) . . m Main Page
- 12:55, 22 July 2016 (diff | hist) . . (+298) . . m What are the data (current)
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