User contributions
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- 15:44, 4 March 2022 (diff | hist) . . (+75) . . Black box, empty box, and unknown box
- 20:05, 10 February 2022 (diff | hist) . . (-66) . . How to save computer resources
- 21:09, 26 January 2022 (diff | hist) . . (-1) . . How to parse a string (current)
- 21:08, 26 January 2022 (diff | hist) . . (-15) . . How to parse a string
- 11:38, 26 January 2022 (diff | hist) . . (+31) . . Notes on analysis
- 12:56, 29 December 2021 (diff | hist) . . (+383) . . Static elaboration
- 21:30, 3 December 2021 (diff | hist) . . (+150) . . System attributes
- 21:26, 3 December 2021 (diff | hist) . . (+135) . . System attributes
- 18:57, 1 December 2021 (diff | hist) . . (+90) . . Black box, empty box, and unknown box
- 17:52, 3 November 2021 (diff | hist) . . (+8) . . Black box, empty box, and unknown box
- 12:38, 27 October 2021 (diff | hist) . . (-21) . . Statically elaborate with different values of parameters (current)
- 12:38, 27 October 2021 (diff | hist) . . (-21) . . Simple example of visitor pattern
- 14:45, 26 October 2021 (diff | hist) . . (+133) . . How to traverse scope hierarchy (current)
- 16:12, 20 October 2021 (diff | hist) . . (-1) . . How to parse a string
- 10:34, 15 October 2021 (diff | hist) . . (-10) . . Main Page
- 10:32, 15 October 2021 (diff | hist) . . (-54) . . How to get best support from Verific
- 09:21, 15 October 2021 (diff | hist) . . (-1) . . Notes on analysis
- 08:52, 15 October 2021 (diff | hist) . . (-1) . . Notes on analysis
- 08:52, 15 October 2021 (diff | hist) . . (+2) . . Notes on analysis
- 08:51, 15 October 2021 (diff | hist) . . (+152) . . Notes on analysis
- 17:49, 14 October 2021 (diff | hist) . . (+1) . . Notes on analysis
- 15:55, 12 October 2021 (diff | hist) . . (+66) . . How to save computer resources
- 11:32, 8 October 2021 (diff | hist) . . (-28) . . Main Page
- 11:31, 8 October 2021 (diff | hist) . . (+108) . . Escaped identifiers in RTL files and in Verific data structures
- 11:13, 8 October 2021 (diff | hist) . . (-33) . . System attributes
- 11:12, 8 October 2021 (diff | hist) . . (+315) . . System attributes
- 20:08, 4 October 2021 (diff | hist) . . (-174) . . Source code customization & Stable release services
- 20:07, 4 October 2021 (diff | hist) . . (+28) . . Source code customization & Stable release services
- 20:06, 4 October 2021 (diff | hist) . . (+3) . . Source code customization & Stable release services
- 19:53, 4 October 2021 (diff | hist) . . (+1) . . Source code customization & Stable release services
- 19:53, 4 October 2021 (diff | hist) . . (+3) . . Source code customization & Stable release services
- 10:07, 30 September 2021 (diff | hist) . . (+3) . . m Source code customization & Stable release services
- 10:00, 30 September 2021 (diff | hist) . . (+206) . . Source code customization & Stable release services
- 09:57, 30 September 2021 (diff | hist) . . (-15) . . Source code customization & Stable release services
- 09:56, 30 September 2021 (diff | hist) . . (+1,763) . . Source code customization & Stable release services
- 09:49, 30 September 2021 (diff | hist) . . (+314) . . N Source code customization & Stable release services (Created page with ">>> Under construction <<< Verific offers two services to licensees: Source Code Customization and Stable Release. On Verific's file system, each of the licensees has a sepa...")
- 09:46, 30 September 2021 (diff | hist) . . (+122) . . Main Page
- 13:59, 28 September 2021 (diff | hist) . . (+3) . . Black box, empty box, and unknown box
- 17:23, 31 August 2021 (diff | hist) . . (+583) . . LineFile data from input files (current)
- 11:39, 9 August 2021 (diff | hist) . . (-1) . . How to get packed dimensions of enum
- 11:39, 9 August 2021 (diff | hist) . . (+714) . . How to get packed dimensions of enum
- 10:24, 6 August 2021 (diff | hist) . . (-265) . . LineFile data from input files
- 09:18, 6 August 2021 (diff | hist) . . (+265) . . LineFile data from input files
- 13:14, 27 July 2021 (diff | hist) . . (+41) . . Accessing and evaluating module's parameters (current)
- 12:44, 27 July 2021 (diff | hist) . . (-4) . . Accessing and evaluating module's parameters
- 12:43, 27 July 2021 (diff | hist) . . (+11) . . Accessing and evaluating module's parameters
- 12:40, 27 July 2021 (diff | hist) . . (+4,589) . . N Accessing and evaluating module's parameters (Created page with " <nowiki> #include "Map.h" #include "Array.h" #include "Strings.h" #include "veri_file.h" #include "VeriBaseValue_Stat.h" #include "VeriModule.h" #include "VeriExpression.h" #...")
- 12:36, 27 July 2021 (diff | hist) . . (+111) . . Main Page
- 12:03, 9 July 2021 (diff | hist) . . (+13) . . Notes on analysis
- 12:03, 9 July 2021 (diff | hist) . . (-3) . . Notes on analysis
- 11:58, 9 July 2021 (diff | hist) . . (-1) . . Notes on analysis
- 10:36, 9 July 2021 (diff | hist) . . (+36) . . Notes on analysis
- 10:31, 9 July 2021 (diff | hist) . . (+39) . . Notes on analysis
- 09:59, 9 July 2021 (diff | hist) . . (+791) . . N Notes on analysis (Created page with "This is a place holder for notes regarding analysis of System Verilog designs. Can I use veri_file::Analyze to read SV input files one by one? Yes. But if you have multiple...")
- 09:52, 9 July 2021 (diff | hist) . . (+59) . . Main Page
- 11:18, 25 June 2021 (diff | hist) . . (+4) . . How to get best support from Verific
- 11:10, 25 June 2021 (diff | hist) . . (+103) . . How to get best support from Verific
- 15:07, 23 June 2021 (diff | hist) . . (+63) . . Remove Verific data structures (current)
- 13:02, 17 June 2021 (diff | hist) . . (+8) . . How to parse a string
- 12:46, 17 June 2021 (diff | hist) . . (+46) . . Main Page
- 12:45, 17 June 2021 (diff | hist) . . (+3) . . How to parse a string
- 12:44, 17 June 2021 (diff | hist) . . (+1,910) . . How to parse a string
- 10:33, 11 June 2021 (diff | hist) . . (-18) . . Defined macros become undefined - MFCU vs SFCU (current)
- 10:33, 11 June 2021 (diff | hist) . . (-51) . . Defined macros become undefined - MFCU vs SFCU
- 10:27, 11 June 2021 (diff | hist) . . (-20) . . How to detect multiple-clock-edge condition in Verilog parsetree (current)
- 10:26, 11 June 2021 (diff | hist) . . (+448) . . How to detect multiple-clock-edge condition in Verilog parsetree
- 10:56, 9 June 2021 (diff | hist) . . (+4,535) . . N How to detect multiple-clock-edge condition in Verilog parsetree (Created page with "Multiple-clock-edge condition is not support for synthesis. For example: always @(posedge clk or negedge clk) out <= in; or in SystemVerilog dialect: always @(ed...")
- 10:43, 9 June 2021 (diff | hist) . . (0) . . Main Page
- 10:41, 9 June 2021 (diff | hist) . . (+151) . . Main Page
- 13:06, 5 May 2021 (diff | hist) . . (+74) . . How to get best support from Verific
- 10:35, 3 May 2021 (diff | hist) . . (-1) . . Remove Verific data structures
- 10:33, 3 May 2021 (diff | hist) . . (-27) . . Remove Verific data structures
- 16:00, 21 April 2021 (diff | hist) . . (+1) . . How Verific elaborator handles blackboxes/unknown boxes (current)
- 11:01, 21 April 2021 (diff | hist) . . (+2,496) . . Simple example of visitor pattern
- 10:58, 21 April 2021 (diff | hist) . . (+1) . . Main Page
- 22:46, 20 April 2021 (diff | hist) . . (0) . . Does Verific support XMR? (current)
- 15:26, 20 April 2021 (diff | hist) . . (+412) . . Pretty-print a module and the packages imported by the module
- 10:08, 20 April 2021 (diff | hist) . . (+128) . . How to get best support from Verific
- 16:11, 19 April 2021 (diff | hist) . . (+1,380) . . Buffering signals and ungrouping (current)
- 16:07, 19 April 2021 (diff | hist) . . (+7,446) . . N Buffering signals and ungrouping (Created page with "During ungrouping (flattening) a hierarchical design, there are nets that need to be merged. The name of the resulting net from the merge will be the name in the highest level...")
- 16:00, 19 April 2021 (diff | hist) . . (+129) . . Main Page
- 11:52, 19 April 2021 (diff | hist) . . (0) . . How to get library containing nested module (current)
- 11:10, 19 April 2021 (diff | hist) . . (+1) . . Main Page
- 11:08, 19 April 2021 (diff | hist) . . (+1,032) . . How to get library containing nested module
- 13:17, 12 April 2021 (diff | hist) . . (+173) . . System attributes
- 13:01, 12 April 2021 (diff | hist) . . (+112) . . System attributes
- 14:17, 8 April 2021 (diff | hist) . . (+5,308) . . N Comment out a line using text based design modification and parsetree modification (Created page with "C++: <nowiki> #include <iostream> #include "veri_file.h" #include "VeriModule.h" #include "VeriStatement.h" #include "Array.h" #include "Strings.h" #include "TextBasedDes...") (current)
- 14:16, 8 April 2021 (diff | hist) . . (0) . . Main Page
- 22:43, 30 March 2021 (diff | hist) . . (+12) . . Main Page
- 22:42, 30 March 2021 (diff | hist) . . (+9,705) . . Where in RTL does it get assigned? (current)
- 14:06, 23 March 2021 (diff | hist) . . (+6,453) . . N Where in RTL does it get assigned? (Created page with "This example illustrates how to find where a signal gets assigned in the RTL code. C++: <nowiki> #include <iostream> #include "veri_file.h" #include "VeriModule.h" #include...")
- 14:06, 23 March 2021 (diff | hist) . . (+2) . . Main Page
- 13:22, 23 March 2021 (diff | hist) . . (+6,453) . . N Where in RTL is it get assigned? (Created page with "This example illustrates how to find where a signal gets assigned in the RTL code. C++: <nowiki> #include <iostream> #include "veri_file.h" #include "VeriModule.h" #include...") (current)
- 13:18, 23 March 2021 (diff | hist) . . (+87) . . Main Page
- 17:05, 18 March 2021 (diff | hist) . . (+5) . . How to save computer resources
- 17:05, 18 March 2021 (diff | hist) . . (-1) . . How to save computer resources
- 17:04, 18 March 2021 (diff | hist) . . (+123) . . How to save computer resources
- 17:02, 18 March 2021 (diff | hist) . . (0) . . How to save computer resources
- 16:30, 18 March 2021 (diff | hist) . . (+293) . . How to save computer resources
- 18:35, 16 March 2021 (diff | hist) . . (+31) . . How to get best support from Verific
- 18:23, 16 March 2021 (diff | hist) . . (0) . . How to get best support from Verific
- 18:11, 16 March 2021 (diff | hist) . . (+127) . . How to get best support from Verific
- 18:02, 16 March 2021 (diff | hist) . . (+190) . . Escaped identifiers in RTL files and in Verific data structures
- 17:57, 16 March 2021 (diff | hist) . . (+73) . . Escaped identifiers in RTL files and in Verific data structures
- 15:15, 16 March 2021 (diff | hist) . . (+13) . . Escaped identifiers in RTL files and in Verific data structures
- 14:57, 16 March 2021 (diff | hist) . . (-4) . . Escaped identifiers in RTL files and in Verific data structures
- 14:57, 16 March 2021 (diff | hist) . . (+38) . . Escaped identifiers in RTL files and in Verific data structures
- 10:29, 16 March 2021 (diff | hist) . . (+27) . . Main Page
- 10:19, 16 March 2021 (diff | hist) . . (+201) . . Escaped identifiers in RTL files and in Verific data structures
- 10:17, 16 March 2021 (diff | hist) . . (+423) . . N Escaped identifiers in RTL files and in Verific data structures (Created page with "'''>>> This page is under construction <<<''' '''Verific data structures: ''' No escaped identifier In netlist outputs and in pretty-print outputs, identifiers are escaped b...")
- 10:11, 16 March 2021 (diff | hist) . . (+151) . . Main Page
- 10:08, 16 March 2021 (diff | hist) . . (+31) . . Main Page
- 10:07, 16 March 2021 (diff | hist) . . (+122) . . How to save computer resources
- 19:36, 15 March 2021 (diff | hist) . . (+234) . . How to save computer resources
- 15:47, 15 March 2021 (diff | hist) . . (+1,615) . . How to get linefile data of macros - Macro callback function
- 15:03, 15 March 2021 (diff | hist) . . (+7) . . Main Page
- 10:04, 15 March 2021 (diff | hist) . . (-67) . . Main Page
- 16:54, 10 March 2021 (diff | hist) . . (+8) . . How to save computer resources
- 16:51, 10 March 2021 (diff | hist) . . (+1,494) . . How to save computer resources
- 15:49, 10 March 2021 (diff | hist) . . (-10) . . Main Page
- 15:48, 10 March 2021 (diff | hist) . . (+252) . . N How to save computer resources (Created page with "'''This page is under construction. ''' - Compile flag VERIFIC_MEMORY_MANAGER - Compile flag DB_USE_PORT_ORDERED_PORTREF - Compile flag VERILOG_QUICK_PARSE_V_FILES - Run...")
- 15:40, 10 March 2021 (diff | hist) . . (+80) . . Main Page
- 17:06, 4 March 2021 (diff | hist) . . (-54) . . Message handling
- 18:12, 25 February 2021 (diff | hist) . . (+14) . . Release version (current)
- 18:11, 25 February 2021 (diff | hist) . . (-2) . . Message handling
- 18:11, 25 February 2021 (diff | hist) . . (-1) . . Message handling
- 18:10, 25 February 2021 (diff | hist) . . (+29) . . Does Verific build CDFG? (current)
- 18:09, 25 February 2021 (diff | hist) . . (+11) . . Does Verific support XMR?
- 15:14, 25 February 2021 (diff | hist) . . (+123) . . Does Verific support XMR?
- 15:11, 25 February 2021 (diff | hist) . . (+4,339) . . N Hierarchy tree RTL elaboration (Created page with "Reference: [https://www.verific.com/faq/index.php?title=Does_Verific_support_XMR%3F Does Verific support XMR?] Synthesizing designs with cross-module referencing needs Hierar...") (current)
- 15:06, 25 February 2021 (diff | hist) . . (+99) . . Main Page
- 21:37, 24 February 2021 (diff | hist) . . (+6) . . How to get best support from Verific
- 18:33, 23 February 2021 (diff | hist) . . (+113) . . Compile-time/run-time flags
- 21:11, 22 February 2021 (diff | hist) . . (+336) . . Replacing Verific built-in primitives/operators with user implementations
- 17:43, 22 February 2021 (diff | hist) . . (-51) . . Replacing Verific built-in primitives/operators with user implementations
- 16:54, 22 February 2021 (diff | hist) . . (+3,480) . . N Replacing Verific built-in primitives/operators with user implementations (Created page with "Below is a C++ application illustrating how to replace Verific's built-in primitives/operators with user implementations. <nowiki> #include <iostream> #include "veri_file.h...")
- 16:39, 22 February 2021 (diff | hist) . . (+170) . . Main Page
- 11:01, 19 February 2021 (diff | hist) . . (+190) . . How to get best support from Verific
- 10:34, 18 February 2021 (diff | hist) . . (+4) . . How to get best support from Verific
- 10:34, 18 February 2021 (diff | hist) . . (+4) . . How to get best support from Verific
- 10:33, 18 February 2021 (diff | hist) . . (+9) . . How to get best support from Verific
- 14:42, 8 February 2021 (diff | hist) . . (-65) . . Release version
- 14:02, 1 February 2021 (diff | hist) . . (+3,820) . . N How to traverse scope hierarchy (Created page with "C++ code: <nowiki> #include <iostream> #include <cstring> // strchr #include "veri_file.h" #include "VeriModule.h" #include "VeriExpression.h" #include "VeriConstVal.h" #inc...")
- 13:54, 1 February 2021 (diff | hist) . . (+85) . . Main Page
- 11:54, 1 February 2021 (diff | hist) . . (+99) . . Tcl library path
- 15:50, 27 January 2021 (diff | hist) . . (+16) . . How to get best support from Verific
- 15:49, 27 January 2021 (diff | hist) . . (-30) . . How to get best support from Verific
- 22:16, 26 January 2021 (diff | hist) . . (+33) . . How to get best support from Verific
- 22:15, 26 January 2021 (diff | hist) . . (+1) . . How to get best support from Verific
- 22:14, 26 January 2021 (diff | hist) . . (+33) . . How to get best support from Verific
- 22:12, 26 January 2021 (diff | hist) . . (0) . . How to get best support from Verific
- 22:11, 26 January 2021 (diff | hist) . . (+39) . . How to get best support from Verific
- 22:10, 26 January 2021 (diff | hist) . . (+227) . . How to get best support from Verific
- 18:59, 26 January 2021 (diff | hist) . . (+138) . . How to get linefile data of macros - Macro callback function
- 18:05, 26 January 2021 (diff | hist) . . (+9,714) . . N How to get linefile data of macros - Macro callback function (Created page with "C++ application: <nowiki> #include <iostream> #include <sstream> #include "veri_file.h" #include "VeriTreeNode.h" #include "Map.h" using namespace std ; #ifdef VERIFIC_N...")
- 18:01, 26 January 2021 (diff | hist) . . (+148) . . Main Page
- 20:20, 7 January 2021 (diff | hist) . . (+10) . . Difference between RTL and gate-level simulations - Flipflop with async set and async reset
- 20:18, 7 January 2021 (diff | hist) . . (-2) . . Difference between RTL and gate-level simulations - Flipflop with async set and async reset
- 15:38, 7 January 2021 (diff | hist) . . (-1) . . Difference between RTL and gate-level simulations - Flipflop with async set and async reset
- 15:36, 7 January 2021 (diff | hist) . . (-3) . . Difference between RTL and gate-level simulations - Flipflop with async set and async reset
- 15:21, 7 January 2021 (diff | hist) . . (+6) . . Difference between RTL and gate-level simulations - Flipflop with async set and async reset
- 15:19, 7 January 2021 (diff | hist) . . (-2) . . Difference between RTL and gate-level simulations - Flipflop with async set and async reset
- 15:15, 7 January 2021 (diff | hist) . . (-98) . . Difference between RTL and gate-level simulations - Flipflop with async set and async reset
- 15:15, 7 January 2021 (diff | hist) . . (+5,337) . . N Difference between RTL and gate-level simulations - Flipflop with async set and async reset (Created page with "'''Difference between RTL and gate-level simulations - Flipflop with async set and async reset''' ''This article is inspired by an article by Clifford E. Cummings and Don Mil...")
- 15:04, 7 January 2021 (diff | hist) . . (+192) . . Main Page
- 13:34, 23 December 2020 (diff | hist) . . (-10) . . Verilog Port Expressions
- 13:33, 23 December 2020 (diff | hist) . . (+10) . . Verilog Port Expressions
- 11:26, 23 December 2020 (diff | hist) . . (+40) . . How Verific elaborator handles blackboxes/unknown boxes
- 10:45, 23 December 2020 (diff | hist) . . (+10) . . How Verific elaborator handles blackboxes/unknown boxes
- 10:00, 23 December 2020 (diff | hist) . . (+861) . . How Verific elaborator handles blackboxes/unknown boxes
- 23:52, 22 December 2020 (diff | hist) . . (-9) . . Black box, empty box, and unknown box
- 23:51, 22 December 2020 (diff | hist) . . (-14) . . How Verific elaborator handles blackboxes/unknown boxes
- 23:50, 22 December 2020 (diff | hist) . . (+14) . . How Verific elaborator handles blackboxes/unknown boxes
- 23:48, 22 December 2020 (diff | hist) . . (+142) . . Black box, empty box, and unknown box
- 23:46, 22 December 2020 (diff | hist) . . (+63) . . How Verific elaborator handles blackboxes/unknown boxes
- 18:45, 22 December 2020 (diff | hist) . . (+3,431) . . N How Verific elaborator handles blackboxes/unknown boxes (Created page with ">> This page is in progress << '''Q: After RTL elaboration on a Verilog design, I see Netlist with names such as 'NamedPorts' or 'OrderedPorts.' Sometimes in the Verilog netl...")
- 18:22, 22 December 2020 (diff | hist) . . (+129) . . Main Page
- 18:18, 22 December 2020 (diff | hist) . . (+10) . . Black box, empty box, and unknown box
- 17:32, 7 December 2020 (diff | hist) . . (+1,033) . . N Simple example of visitor pattern (Created page with " <nowiki> $ cat test.cpp #include <iostream> #include "veri_file.h" #include "VeriModule.h" #include "VeriVisitor.h" #include "VeriConstVal.h" #include "Strings.h" #ifdef V...")
- 17:29, 7 December 2020 (diff | hist) . . (+89) . . Main Page
- 13:49, 7 December 2020 (diff | hist) . . (+2,605) . . N Access attributes in parsetree (Created page with " <nowiki> #include "veri_file.h" #include "VeriModule.h" #include "VeriExpression.h" #include "VeriMisc.h" #include "VeriId.h" #include "Map.h" #include "Array.h" #include "...")
- 13:45, 7 December 2020 (diff | hist) . . (+90) . . Main Page
- 13:18, 7 December 2020 (diff | hist) . . (+242) . . Message handling
- 23:14, 17 November 2020 (diff | hist) . . (+224) . . How to get best support from Verific
- 16:09, 13 November 2020 (diff | hist) . . (+5) . . Main Page
- 16:07, 13 November 2020 (diff | hist) . . (+5,187) . . Type Range example with multi-dimensional arrays (current)
- 15:45, 7 October 2020 (diff | hist) . . (+22) . . LineFile data from input files
- 15:15, 1 October 2020 (diff | hist) . . (+2,137) . . N LineFile data from input files (Created page with "Verific uses the 'LineFile' manager to preserve line/file origination information from HDL source files. This info is annotated on all objects in parse trees and netlist datab...")
- 15:04, 1 October 2020 (diff | hist) . . (+70) . . Main Page
- 14:20, 15 September 2020 (diff | hist) . . (+8) . . How to get best support from Verific
- 12:05, 4 September 2020 (diff | hist) . . (+5) . . Simulation models for Verific primitives (current)
- 12:04, 4 September 2020 (diff | hist) . . (+98) . . N Simulation models for Verific primitives (Created page with "They are in example_designs/verilog/verificmodels.v and example_designs/verilog/verificsvamodels.v")
- 12:03, 4 September 2020 (diff | hist) . . (+143) . . Main Page
- 15:25, 24 August 2020 (diff | hist) . . (+5,984) . . N Fanout cone and grouping (Created page with "C++ code: <nowiki> →This application example collects instances in the fanout cone of a signal, and groups those instances into a new netlist: #include "Set.h" #include...")
- 15:20, 24 August 2020 (diff | hist) . . (+105) . . Main Page
- 10:39, 6 August 2020 (diff | hist) . . (+1,269) . . How to change name of id in Verilog parsetree
- 17:27, 30 July 2020 (diff | hist) . . (+800) . . Black box, empty box, and unknown box
- 17:06, 22 July 2020 (diff | hist) . . (+1,585) . . Included files associated with a Verilog source file (current)
- 16:44, 22 July 2020 (diff | hist) . . (+6) . . Included files associated with a Verilog source file
- 14:49, 20 July 2020 (diff | hist) . . (+2,448) . . N How to parse a string (Created page with "Let's say you want to add a node to the parsetree. One of the simple ways to do so is to start with a text string; then "parse" that string to get a VHDL or Verilog construct...")
- 14:29, 20 July 2020 (diff | hist) . . (+66) . . Main Page
- 14:10, 9 July 2020 (diff | hist) . . (+793) . . Access attributes of ports in parsetree (current)
- 13:01, 23 June 2020 (diff | hist) . . (+2,705) . . N How to create new module in Verilog parsetree (Created page with "This code sample also shows how to add new parameters and new ports to a module. C++: <nowiki> #include <iostream> #include "veri_file.h" #include "veri_tokens.h" #include...") (current)
- 12:58, 23 June 2020 (diff | hist) . . (+113) . . Main Page
- 12:31, 23 June 2020 (diff | hist) . . (+5,317) . . N How to get full hierarchy ID path (Created page with "Note that this code sample requires "Hierarchy Tree" feature. C++ code: <nowiki> #include "VerificSystem.h" #include "veri_file.h" #include "VeriModuleItem.h" #include "Veri...") (current)
- 12:30, 23 June 2020 (diff | hist) . . (-2) . . Main Page
- 12:24, 23 June 2020 (diff | hist) . . (+5,317) . . N Verilog/C++: How to get full hiererachy ID path : How to get full hiererachy ID path (Created page with "Note that this code sample requires "Hierarchy Tree" feature. C++ code: <nowiki> #include "VerificSystem.h" #include "veri_file.h" #include "VeriModuleItem.h" #include "Veri...") (current)
- 12:20, 23 June 2020 (diff | hist) . . (+91) . . Main Page
- 01:36, 15 June 2020 (diff | hist) . . (-300) . . System attributes
- 18:02, 5 June 2020 (diff | hist) . . (+3,126) . . Create a Netlist Database from scratch (not from RTL elaboration)
- 17:58, 5 June 2020 (diff | hist) . . (+4) . . Main Page
- 14:08, 5 June 2020 (diff | hist) . . (-128) . . Black box, empty box, and unknown box
- 17:44, 4 June 2020 (diff | hist) . . (+32) . . Black box, empty box, and unknown box
- 14:49, 4 June 2020 (diff | hist) . . (+11) . . Black box, empty box, and unknown box
- 14:43, 4 June 2020 (diff | hist) . . (+7,550) . . N Black box, empty box, and unknown box (Created page with "In Verific Netlist Database, a Netlist can be a black box, an empty box, or an unknown box. #An unknown box is a Netlist that is #*from an instantiation of an undefined Veril...")
- 14:07, 4 June 2020 (diff | hist) . . (+98) . . Main Page
- 17:47, 2 June 2020 (diff | hist) . . (+2,399) . . Message handling
- 17:29, 2 June 2020 (diff | hist) . . (+40) . . Main Page
- 14:12, 1 June 2020 (diff | hist) . . (+1,657) . . N Parsing from data in memory (Created page with "It is possible to use "stream input" to parse data in memory. The example below is For Verilog input, but it can be adapted to use for VHLD input as well. If you run this ap...") (current)
- 14:07, 1 June 2020 (diff | hist) . . (+82) . . Main Page
- 14:44, 14 May 2020 (diff | hist) . . (+49) . . How to use RegisterCallBackMsg() (current)
- 13:30, 14 May 2020 (diff | hist) . . (+3,157) . . N How to use RegisterCallBackMsg() (Created page with "Here is a small example showing how to use RegisterCallBackMsg(): <nowiki> #include <stdio.h> #include <stdarg.h> #include "Strings.h" #include "Map.h" // Make assoc...")
- 13:25, 14 May 2020 (diff | hist) . . (+84) . . Main Page
- 15:19, 13 May 2020 (diff | hist) . . (-10) . . Main Page
- 15:18, 13 May 2020 (diff | hist) . . (+10) . . Main Page
- 20:05, 8 May 2020 (diff | hist) . . (+1) . . System attributes
- 20:03, 8 May 2020 (diff | hist) . . (+12) . . System attributes
- 13:40, 6 May 2020 (diff | hist) . . (+2) . . What VeriModule* or VhdlPrimaryUnit* the Netlist comes from? (current)
- 13:40, 6 May 2020 (diff | hist) . . (+19) . . What VeriModule* or VhdlPrimaryUnit* the Netlist comes from?
- 13:03, 6 May 2020 (diff | hist) . . (+1) . . Macro Callback example (current)
- 13:12, 28 April 2020 (diff | hist) . . (-2) . . How to get best support from Verific
- 13:11, 28 April 2020 (diff | hist) . . (+318) . . How to get best support from Verific
- 11:09, 28 April 2020 (diff | hist) . . (-4) . . How to get best support from Verific
- 12:06, 26 March 2020 (diff | hist) . . (+39) . . Does Verific support XMR?
- 19:03, 14 February 2020 (diff | hist) . . (+30) . . System attributes
- 12:36, 14 February 2020 (diff | hist) . . (-4) . . System attributes
- 12:35, 14 February 2020 (diff | hist) . . (+2) . . System attributes
- 12:33, 14 February 2020 (diff | hist) . . (+323) . . System attributes
- 12:08, 14 February 2020 (diff | hist) . . (+4) . . System attributes
- 12:07, 14 February 2020 (diff | hist) . . (+2) . . System attributes
- 15:20, 13 February 2020 (diff | hist) . . (+46) . . System attributes
- 14:42, 13 February 2020 (diff | hist) . . (-1) . . System attributes
- 14:42, 13 February 2020 (diff | hist) . . (-40) . . System attributes
- 14:41, 13 February 2020 (diff | hist) . . (+2,540) . . N System attributes (Created page with "Verific system attributes are attributes added and attached to DesignObjs (Design Objects) during the process of building the Netlist Database. To distinguish with user-decla...")
- 14:27, 13 February 2020 (diff | hist) . . (+62) . . Main Page
- 17:04, 12 February 2020 (diff | hist) . . (+2,764) . . N Using stream input to ignore input file (Created page with "This example shows how to use stream input to ignore input files that meet certain conditions. The example uses only filename as the "ignore" category. But you can have other...") (current)
- 16:59, 12 February 2020 (diff | hist) . . (+101) . . Main Page
- 16:02, 10 February 2020 (diff | hist) . . (+9,156) . . N Bit-blasting a multi-port RAM instance (Created page with "'''Q: What is bit-blasting a multi-port RAM instance''' Verific’s RAM extraction creates a minimal-port, multi-port RAM model in the netlist for every identifier that behav...") (current)
- 15:55, 10 February 2020 (diff | hist) . . (+103) . . Main Page
- 18:30, 3 February 2020 (diff | hist) . . (+8) . . Main Page
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