Illinois Institute of Technology (Illinois Tech) alumnus Rick Carlson (MATH ’70), vice president of sales for Verific Design Automation, a leading provider of SystemVerilog, Verilog, VHDL, and UPF Parser Platforms, has been elected to the College of Computing Board of Advisors.
An internal computer aided design (CAD) or design services engineer is responsible for delivering efficient, robust and high-quality design flow solutions. The design flow on a day-to-day basis keeps chip designers and verification engineers productive and focused on their jobs, preventing them from debugging CAD tools and flows and creating ad hoc and undocumented scripts. Over the life of a project, a high-quality design flow differentiates a company from competitors and can be the difference between getting chips to market first or being the victim of unexpected process bottleneck and delays.
Verific is an unusual company. They are completely dominant in what they do – providing parsers for Verilog/SV, VHDL and UPF. Yet they have no ambition to expand beyond that goal. Instead, per Michiel Ligthart (President and COO), they continue to “sharpen the saw”. This is an expression I learned in sales training, habit #7 from 7 Habits of Highly Effective People. Constantly refining and polishing (or sharpening) the tools you already have rather than launching out into building new tools. That’s a great way to keep existing customers loyal and to steadily grow a business. They are still investing in interesting development, but it is all around these core tools.
Verific Design Automation, the leading provider of SystemVerilog, Verilog, VHDL and UPF Parser Platforms, today announced Rapid Silicon, a provider of AI-enabled application-specific FPGAs based on open-source technology, is the newest licensee of its Parser Platform.