Verific Design Automation today announced immediate availability of a parser for the IEEE 1801-2009 Standard for Design and Verification of Low-Power Integrated Circuits. Also known as Unified Power Format 2.0 (UPF 2.0), it was developed by standards organization Accellera and carries the support of multiple EDA vendors.
Do-It-Yourself EDA Flows Take Off in 2012
When Verific started providing (System)Verilog and VHDL parsers in 2001, EDA companies were quick to jump on the bandwagon. Semiconductor companies with internal CAD teams and FPGA companies supporting customer design tools followed suit when they realized that they would be better off re-using Verific’s parsers than build their own.
vSync Circuits licenses Verific’s Parser Platform
Verific Design Automation, supplier of industry-standard, IEEE-compliant hardware description language (HDL) front-end solutions, today announced vSync Circuits Ltd. in Israel has licensed its parser platform for use with the vSync clock domain crossing (CDC) verification software.
Verific unveils Perl interface for its SystemVerilog and VHDL front-end solutions
The folks at Verific Design Automation, long known for their SystemVerilog and VHDL front-end solutions used by leading EDA, FPGA and semiconductor companies worldwide, have just unveiled a Perl interface to their industry-standard, IEEE-compliant SystemVerilog and VHDL parsers and elaborators.
Ausdia Licenses Verific’s Parser Platform
Ausdia Inc., provider of chip design and closure solutions, has licensed Verific Design Automation’s Verilog parser platform for use with its analysis and optimization software for accelerating timing constraint development, constraint validation and timing closure.”When we looked for a platform for RTL analysis, we quickly realized that the only answer was Verific,” says Sam Appleton, Ausdia’s chief executive officer (CEO).