Verific Design Automation, provider of SystemVerilog, Verilog and VHDL parsers, closed 2013 with a double-digit increase in revenue and56 active user companies, many of whom are longstanding customers.
Tabula upgrades to SystemVerilog
Verific Design Automation, provider of SystemVerilog, Verilog and VHDL parsers, today announced that Tabula (www.tabula.com) has added Verific’s SystemVerilog parser as front-end support to version 2.7.1 of its Stylus® compiler.
Verific increases revenue by 20%
Verific Design Automation, provider of SystemVerilog, Verilog and VHDL parsers, ended 2012 with 52 active user companies and a revenue increase of 20% over 2011.
Aldec partners with Verific for HES platform
Verific Design Automation today announced it licensed its industry-standard, IEEE-compliant SystemVerilog and VHDL platform to Aldec, Inc.,a global leader in electronic design verification, to be included into its Hardware Emulation Solution (HES™).
Excellicon’s ConMan uses Verific
Excellicon, a first-time exhibitor of end-to-end Timing Constraints Solution at the Design Automation Conference (DAC), today announced it adopted Verific Design Automation’s industry-standard, IEEE-compliant front-end platform for use with its software for timing constraints authoring, verification and management.
- « Previous Page
- 1
- …
- 10
- 11
- 12
- 13
- 14
- 15
- Next Page »