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- 14:22, 6 April 2017 (diff | hist) . . (+385) . . N Instance - Module binding order (Created page with "'''Q: Verilog has many ways to find modules not in the file being directly read: -L, -v, -y, .... There may be more than one module of the same name. What is the order of bind...")
- 14:16, 6 April 2017 (diff | hist) . . (+100) . . Main Page
- 13:42, 6 April 2017 (diff | hist) . . (+741) . . N How to find port dimensions (Created page with "'''Q: How do I get port dimensions?''' A port can have multiple (packed/unpacked) dimensions like "module test (input [1:0][2:3] in1 [4:5][6:7]);". Below is a code excerpt in...") (current)
- 13:39, 6 April 2017 (diff | hist) . . (+75) . . Main Page
- 15:33, 5 April 2017 (diff | hist) . . (+836) . . N How to get library containing nested module (Created page with "'''Q: How do I get the library that contains the module nested inside another module?''' Take the following example: 1 module top (output o, input i1, i2, i3); 2 logic...")
- 15:26, 5 April 2017 (diff | hist) . . (+141) . . Main Page
- 11:55, 5 April 2017 (diff | hist) . . (+3) . . What languages can I use with Verific software?
- 15:45, 22 March 2017 (diff | hist) . . (+1,896) . . N How to get linefile information of macro definitions (Created page with "'''Q: How do I get linefile information of macro definitions?''' Take the following example: 1 `define A 2 `define B 10 3 `define C(a) a 4 `define D(a, b) a + b 5...") (current)
- 15:31, 22 March 2017 (diff | hist) . . (+126) . . m Main Page
- 14:03, 16 March 2017 (diff | hist) . . (-85) . . Does Verific support XMR?
- 12:29, 10 February 2017 (diff | hist) . . (+1) . . How to change name of id in Verilog parsetree
- 12:29, 10 February 2017 (diff | hist) . . (+433) . . N How to change name of id in Verilog parsetree (Created page with "'''Q:How do I change the name of an id (VeriIdDef) in Verilog parsetree?''' Name of identifier can be changed using following steps: 1. Get the scope where identifier is dec...")
- 12:23, 10 February 2017 (diff | hist) . . (+131) . . m Main Page
- 12:20, 8 December 2016 (diff | hist) . . (+145) . . m Original RTL language (current)
- 11:50, 29 November 2016 (diff | hist) . . (+10) . . m What VeriModule* or VhdlPrimaryUnit* the Netlist comes from?
- 11:48, 29 November 2016 (diff | hist) . . (-1) . . m Main Page
- 11:47, 29 November 2016 (diff | hist) . . (+11) . . m Main Page
- 11:44, 29 November 2016 (diff | hist) . . (+9) . . m Design with VHDL-1993 and VHDL-2008 files (current)
- 11:42, 29 November 2016 (diff | hist) . . (+1) . . SystemVerilog "std" package
- 11:42, 29 November 2016 (diff | hist) . . (+6) . . Constant expression replacement
- 11:39, 29 November 2016 (diff | hist) . . (+14) . . Compile-time/run-time flags
- 11:37, 29 November 2016 (diff | hist) . . (+1) . . Design with System Verilog and Verilog 2001 files
- 11:27, 29 November 2016 (diff | hist) . . (+607) . . m Message handling
- 10:53, 29 November 2016 (diff | hist) . . (+135) . . m Remove Verific data structures
- 13:50, 23 November 2016 (diff | hist) . . (-5) . . m Remove Verific data structures
- 15:29, 22 November 2016 (diff | hist) . . (+910) . . m How to get all Verilog files being analyzed
- 14:55, 26 October 2016 (diff | hist) . . (+1,842) . . N How to get type/initial value of parameters (Created page with "'''Q: Why do I get type and initial value of parameters?''' Example Perl code: #!/usr/bin/perl # push(@INC,"../../../perlmain/install"); require "Verific.pm"; #...")
- 14:49, 26 October 2016 (diff | hist) . . (+106) . . Main Page
- 14:43, 26 October 2016 (diff | hist) . . (+90) . . Main Page
- 14:43, 26 October 2016 (diff | hist) . . (+430) . . N Prettyprint to a string (Created page with "'''Q: Why do I prettyprint a Verilog parsetree node to a string?''' Example code: VeriExpression *init_value = param_id -> GetInitialValue(); if (init_value)...")
- 10:49, 22 September 2016 (diff | hist) . . (+413) . . m Does Verific support XMR?
- 15:15, 4 August 2016 (diff | hist) . . (+5) . . m Main Page
- 15:14, 4 August 2016 (diff | hist) . . (+602) . . N Message handling (Created page with "'''Q: How do I upgrade/downgrade messages from Verific?''' For C++, use the following APIs: Message::SetMessageType() - Force a message type by message id Message::Ge...")
- 15:08, 4 August 2016 (diff | hist) . . (+71) . . m Main Page
- 15:33, 1 August 2016 (diff | hist) . . (+1) . . Constant expression replacement
- 15:32, 1 August 2016 (diff | hist) . . (+495) . . N Constant expression replacement (Created page with "'''Q: Does Verific replace constant expressions with their respective values?''' I have in my Verilog code: parameter size = 8; reg [size-1:0] foo; I expect the range...")
- 15:28, 1 August 2016 (diff | hist) . . (+121) . . m Main Page
- 10:43, 28 July 2016 (diff | hist) . . (-12) . . Remove Verific data structures
- 10:42, 28 July 2016 (diff | hist) . . (-32) . . m Remove Verific data structures
- 10:41, 28 July 2016 (diff | hist) . . (+24) . . m Remove Verific data structures
- 15:13, 27 July 2016 (diff | hist) . . (+11) . . m Main Page
- 15:12, 27 July 2016 (diff | hist) . . (+879) . . N SystemVerilog "std" package (Created page with "'''Q: Support for SystemVerilog semaphore/process/mailbox.''' When I analyzed my SystemVerilog file, Verific issued error message: test.sv(4): ERROR: process is not declare...")
- 15:05, 27 July 2016 (diff | hist) . . (+1) . . m Main Page
- 15:04, 27 July 2016 (diff | hist) . . (+97) . . m Main Page
- 15:02, 27 July 2016 (diff | hist) . . (+21) . . m Main Page
- 15:02, 27 July 2016 (diff | hist) . . (0) . . m Main Page
- 15:00, 27 July 2016 (diff | hist) . . (+65) . . m Main Page
- 14:46, 27 July 2016 (diff | hist) . . (-2) . . m Compile-time/run-time flags
- 14:40, 27 July 2016 (diff | hist) . . (+3) . . Compile-time/run-time flags
- 14:39, 27 July 2016 (diff | hist) . . (+790) . . N Compile-time/run-time flags (Created page with "'''Q: Are there options to control Verific software's behavior?''' There are compile-time flags and run-time flags to control Verific software's behavior. The compile-time f...")
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