User contributions
(newest | oldest) View (newer 250 | older 250) (20 | 50 | 100 | 250 | 500)
- 13:18, 23 March 2021 (diff | hist) . . (+87) . . Main Page
- 17:05, 18 March 2021 (diff | hist) . . (+5) . . How to save computer resources
- 17:05, 18 March 2021 (diff | hist) . . (-1) . . How to save computer resources
- 17:04, 18 March 2021 (diff | hist) . . (+123) . . How to save computer resources
- 17:02, 18 March 2021 (diff | hist) . . (0) . . How to save computer resources
- 16:30, 18 March 2021 (diff | hist) . . (+293) . . How to save computer resources
- 18:35, 16 March 2021 (diff | hist) . . (+31) . . How to get best support from Verific
- 18:23, 16 March 2021 (diff | hist) . . (0) . . How to get best support from Verific
- 18:11, 16 March 2021 (diff | hist) . . (+127) . . How to get best support from Verific
- 18:02, 16 March 2021 (diff | hist) . . (+190) . . Escaped identifiers in RTL files and in Verific data structures
- 17:57, 16 March 2021 (diff | hist) . . (+73) . . Escaped identifiers in RTL files and in Verific data structures
- 15:15, 16 March 2021 (diff | hist) . . (+13) . . Escaped identifiers in RTL files and in Verific data structures
- 14:57, 16 March 2021 (diff | hist) . . (-4) . . Escaped identifiers in RTL files and in Verific data structures
- 14:57, 16 March 2021 (diff | hist) . . (+38) . . Escaped identifiers in RTL files and in Verific data structures
- 10:29, 16 March 2021 (diff | hist) . . (+27) . . Main Page
- 10:19, 16 March 2021 (diff | hist) . . (+201) . . Escaped identifiers in RTL files and in Verific data structures
- 10:17, 16 March 2021 (diff | hist) . . (+423) . . N Escaped identifiers in RTL files and in Verific data structures (Created page with "'''>>> This page is under construction <<<''' '''Verific data structures: ''' No escaped identifier In netlist outputs and in pretty-print outputs, identifiers are escaped b...")
- 10:11, 16 March 2021 (diff | hist) . . (+151) . . Main Page
- 10:08, 16 March 2021 (diff | hist) . . (+31) . . Main Page
- 10:07, 16 March 2021 (diff | hist) . . (+122) . . How to save computer resources
- 19:36, 15 March 2021 (diff | hist) . . (+234) . . How to save computer resources
- 15:47, 15 March 2021 (diff | hist) . . (+1,615) . . How to get linefile data of macros - Macro callback function
- 15:03, 15 March 2021 (diff | hist) . . (+7) . . Main Page
- 10:04, 15 March 2021 (diff | hist) . . (-67) . . Main Page
- 16:54, 10 March 2021 (diff | hist) . . (+8) . . How to save computer resources
- 16:51, 10 March 2021 (diff | hist) . . (+1,494) . . How to save computer resources
- 15:49, 10 March 2021 (diff | hist) . . (-10) . . Main Page
- 15:48, 10 March 2021 (diff | hist) . . (+252) . . N How to save computer resources (Created page with "'''This page is under construction. ''' - Compile flag VERIFIC_MEMORY_MANAGER - Compile flag DB_USE_PORT_ORDERED_PORTREF - Compile flag VERILOG_QUICK_PARSE_V_FILES - Run...")
- 15:40, 10 March 2021 (diff | hist) . . (+80) . . Main Page
- 17:06, 4 March 2021 (diff | hist) . . (-54) . . Message handling
- 18:12, 25 February 2021 (diff | hist) . . (+14) . . Release version (current)
- 18:11, 25 February 2021 (diff | hist) . . (-2) . . Message handling
- 18:11, 25 February 2021 (diff | hist) . . (-1) . . Message handling
- 18:10, 25 February 2021 (diff | hist) . . (+29) . . Does Verific build CDFG? (current)
- 18:09, 25 February 2021 (diff | hist) . . (+11) . . Does Verific support XMR?
- 15:14, 25 February 2021 (diff | hist) . . (+123) . . Does Verific support XMR?
- 15:11, 25 February 2021 (diff | hist) . . (+4,339) . . N Hierarchy tree RTL elaboration (Created page with "Reference: [https://www.verific.com/faq/index.php?title=Does_Verific_support_XMR%3F Does Verific support XMR?] Synthesizing designs with cross-module referencing needs Hierar...") (current)
- 15:06, 25 February 2021 (diff | hist) . . (+99) . . Main Page
- 21:37, 24 February 2021 (diff | hist) . . (+6) . . How to get best support from Verific
- 18:33, 23 February 2021 (diff | hist) . . (+113) . . Compile-time/run-time flags
- 21:11, 22 February 2021 (diff | hist) . . (+336) . . Replacing Verific built-in primitives/operators with user implementations
- 17:43, 22 February 2021 (diff | hist) . . (-51) . . Replacing Verific built-in primitives/operators with user implementations
- 16:54, 22 February 2021 (diff | hist) . . (+3,480) . . N Replacing Verific built-in primitives/operators with user implementations (Created page with "Below is a C++ application illustrating how to replace Verific's built-in primitives/operators with user implementations. <nowiki> #include <iostream> #include "veri_file.h...")
- 16:39, 22 February 2021 (diff | hist) . . (+170) . . Main Page
- 11:01, 19 February 2021 (diff | hist) . . (+190) . . How to get best support from Verific
- 10:34, 18 February 2021 (diff | hist) . . (+4) . . How to get best support from Verific
- 10:34, 18 February 2021 (diff | hist) . . (+4) . . How to get best support from Verific
- 10:33, 18 February 2021 (diff | hist) . . (+9) . . How to get best support from Verific
- 14:42, 8 February 2021 (diff | hist) . . (-65) . . Release version
- 14:02, 1 February 2021 (diff | hist) . . (+3,820) . . N How to traverse scope hierarchy (Created page with "C++ code: <nowiki> #include <iostream> #include <cstring> // strchr #include "veri_file.h" #include "VeriModule.h" #include "VeriExpression.h" #include "VeriConstVal.h" #inc...")
- 13:54, 1 February 2021 (diff | hist) . . (+85) . . Main Page
- 11:54, 1 February 2021 (diff | hist) . . (+99) . . Tcl library path
- 15:50, 27 January 2021 (diff | hist) . . (+16) . . How to get best support from Verific
- 15:49, 27 January 2021 (diff | hist) . . (-30) . . How to get best support from Verific
- 22:16, 26 January 2021 (diff | hist) . . (+33) . . How to get best support from Verific
- 22:15, 26 January 2021 (diff | hist) . . (+1) . . How to get best support from Verific
- 22:14, 26 January 2021 (diff | hist) . . (+33) . . How to get best support from Verific
- 22:12, 26 January 2021 (diff | hist) . . (0) . . How to get best support from Verific
- 22:11, 26 January 2021 (diff | hist) . . (+39) . . How to get best support from Verific
- 22:10, 26 January 2021 (diff | hist) . . (+227) . . How to get best support from Verific
- 18:59, 26 January 2021 (diff | hist) . . (+138) . . How to get linefile data of macros - Macro callback function
- 18:05, 26 January 2021 (diff | hist) . . (+9,714) . . N How to get linefile data of macros - Macro callback function (Created page with "C++ application: <nowiki> #include <iostream> #include <sstream> #include "veri_file.h" #include "VeriTreeNode.h" #include "Map.h" using namespace std ; #ifdef VERIFIC_N...")
- 18:01, 26 January 2021 (diff | hist) . . (+148) . . Main Page
- 20:20, 7 January 2021 (diff | hist) . . (+10) . . Difference between RTL and gate-level simulations - Flipflop with async set and async reset
- 20:18, 7 January 2021 (diff | hist) . . (-2) . . Difference between RTL and gate-level simulations - Flipflop with async set and async reset
- 15:38, 7 January 2021 (diff | hist) . . (-1) . . Difference between RTL and gate-level simulations - Flipflop with async set and async reset
- 15:36, 7 January 2021 (diff | hist) . . (-3) . . Difference between RTL and gate-level simulations - Flipflop with async set and async reset
- 15:21, 7 January 2021 (diff | hist) . . (+6) . . Difference between RTL and gate-level simulations - Flipflop with async set and async reset
- 15:19, 7 January 2021 (diff | hist) . . (-2) . . Difference between RTL and gate-level simulations - Flipflop with async set and async reset
- 15:15, 7 January 2021 (diff | hist) . . (-98) . . Difference between RTL and gate-level simulations - Flipflop with async set and async reset
- 15:15, 7 January 2021 (diff | hist) . . (+5,337) . . N Difference between RTL and gate-level simulations - Flipflop with async set and async reset (Created page with "'''Difference between RTL and gate-level simulations - Flipflop with async set and async reset''' ''This article is inspired by an article by Clifford E. Cummings and Don Mil...")
- 15:04, 7 January 2021 (diff | hist) . . (+192) . . Main Page
- 13:34, 23 December 2020 (diff | hist) . . (-10) . . Verilog Port Expressions
- 13:33, 23 December 2020 (diff | hist) . . (+10) . . Verilog Port Expressions
- 11:26, 23 December 2020 (diff | hist) . . (+40) . . How Verific elaborator handles blackboxes/unknown boxes
- 10:45, 23 December 2020 (diff | hist) . . (+10) . . How Verific elaborator handles blackboxes/unknown boxes
- 10:00, 23 December 2020 (diff | hist) . . (+861) . . How Verific elaborator handles blackboxes/unknown boxes
- 23:52, 22 December 2020 (diff | hist) . . (-9) . . Black box, empty box, and unknown box
- 23:51, 22 December 2020 (diff | hist) . . (-14) . . How Verific elaborator handles blackboxes/unknown boxes
- 23:50, 22 December 2020 (diff | hist) . . (+14) . . How Verific elaborator handles blackboxes/unknown boxes
- 23:48, 22 December 2020 (diff | hist) . . (+142) . . Black box, empty box, and unknown box
- 23:46, 22 December 2020 (diff | hist) . . (+63) . . How Verific elaborator handles blackboxes/unknown boxes
- 18:45, 22 December 2020 (diff | hist) . . (+3,431) . . N How Verific elaborator handles blackboxes/unknown boxes (Created page with ">> This page is in progress << '''Q: After RTL elaboration on a Verilog design, I see Netlist with names such as 'NamedPorts' or 'OrderedPorts.' Sometimes in the Verilog netl...")
- 18:22, 22 December 2020 (diff | hist) . . (+129) . . Main Page
- 18:18, 22 December 2020 (diff | hist) . . (+10) . . Black box, empty box, and unknown box
- 17:32, 7 December 2020 (diff | hist) . . (+1,033) . . N Simple example of visitor pattern (Created page with " <nowiki> $ cat test.cpp #include <iostream> #include "veri_file.h" #include "VeriModule.h" #include "VeriVisitor.h" #include "VeriConstVal.h" #include "Strings.h" #ifdef V...")
- 17:29, 7 December 2020 (diff | hist) . . (+89) . . Main Page
- 13:49, 7 December 2020 (diff | hist) . . (+2,605) . . N Access attributes in parsetree (Created page with " <nowiki> #include "veri_file.h" #include "VeriModule.h" #include "VeriExpression.h" #include "VeriMisc.h" #include "VeriId.h" #include "Map.h" #include "Array.h" #include "...")
- 13:45, 7 December 2020 (diff | hist) . . (+90) . . Main Page
- 13:18, 7 December 2020 (diff | hist) . . (+242) . . Message handling
- 23:14, 17 November 2020 (diff | hist) . . (+224) . . How to get best support from Verific
- 16:09, 13 November 2020 (diff | hist) . . (+5) . . Main Page
- 16:07, 13 November 2020 (diff | hist) . . (+5,187) . . Type Range example with multi-dimensional arrays (current)
- 15:45, 7 October 2020 (diff | hist) . . (+22) . . LineFile data from input files
- 15:15, 1 October 2020 (diff | hist) . . (+2,137) . . N LineFile data from input files (Created page with "Verific uses the 'LineFile' manager to preserve line/file origination information from HDL source files. This info is annotated on all objects in parse trees and netlist datab...")
- 15:04, 1 October 2020 (diff | hist) . . (+70) . . Main Page
- 14:20, 15 September 2020 (diff | hist) . . (+8) . . How to get best support from Verific
- 12:05, 4 September 2020 (diff | hist) . . (+5) . . Simulation models for Verific primitives (current)
- 12:04, 4 September 2020 (diff | hist) . . (+98) . . N Simulation models for Verific primitives (Created page with "They are in example_designs/verilog/verificmodels.v and example_designs/verilog/verificsvamodels.v")
- 12:03, 4 September 2020 (diff | hist) . . (+143) . . Main Page
- 15:25, 24 August 2020 (diff | hist) . . (+5,984) . . N Fanout cone and grouping (Created page with "C++ code: <nowiki> →This application example collects instances in the fanout cone of a signal, and groups those instances into a new netlist: #include "Set.h" #include...")
- 15:20, 24 August 2020 (diff | hist) . . (+105) . . Main Page
- 10:39, 6 August 2020 (diff | hist) . . (+1,269) . . How to change name of id in Verilog parsetree
- 17:27, 30 July 2020 (diff | hist) . . (+800) . . Black box, empty box, and unknown box
- 17:06, 22 July 2020 (diff | hist) . . (+1,585) . . Included files associated with a Verilog source file (current)
- 16:44, 22 July 2020 (diff | hist) . . (+6) . . Included files associated with a Verilog source file
- 14:49, 20 July 2020 (diff | hist) . . (+2,448) . . N How to parse a string (Created page with "Let's say you want to add a node to the parsetree. One of the simple ways to do so is to start with a text string; then "parse" that string to get a VHDL or Verilog construct...")
- 14:29, 20 July 2020 (diff | hist) . . (+66) . . Main Page
- 14:10, 9 July 2020 (diff | hist) . . (+793) . . Access attributes of ports in parsetree (current)
- 13:01, 23 June 2020 (diff | hist) . . (+2,705) . . N How to create new module in Verilog parsetree (Created page with "This code sample also shows how to add new parameters and new ports to a module. C++: <nowiki> #include <iostream> #include "veri_file.h" #include "veri_tokens.h" #include...") (current)
- 12:58, 23 June 2020 (diff | hist) . . (+113) . . Main Page
- 12:31, 23 June 2020 (diff | hist) . . (+5,317) . . N How to get full hierarchy ID path (Created page with "Note that this code sample requires "Hierarchy Tree" feature. C++ code: <nowiki> #include "VerificSystem.h" #include "veri_file.h" #include "VeriModuleItem.h" #include "Veri...") (current)
- 12:30, 23 June 2020 (diff | hist) . . (-2) . . Main Page
- 12:24, 23 June 2020 (diff | hist) . . (+5,317) . . N Verilog/C++: How to get full hiererachy ID path : How to get full hiererachy ID path (Created page with "Note that this code sample requires "Hierarchy Tree" feature. C++ code: <nowiki> #include "VerificSystem.h" #include "veri_file.h" #include "VeriModuleItem.h" #include "Veri...") (current)
- 12:20, 23 June 2020 (diff | hist) . . (+91) . . Main Page
- 01:36, 15 June 2020 (diff | hist) . . (-300) . . System attributes
- 18:02, 5 June 2020 (diff | hist) . . (+3,126) . . Create a Netlist Database from scratch (not from RTL elaboration)
- 17:58, 5 June 2020 (diff | hist) . . (+4) . . Main Page
- 14:08, 5 June 2020 (diff | hist) . . (-128) . . Black box, empty box, and unknown box
- 17:44, 4 June 2020 (diff | hist) . . (+32) . . Black box, empty box, and unknown box
- 14:49, 4 June 2020 (diff | hist) . . (+11) . . Black box, empty box, and unknown box
- 14:43, 4 June 2020 (diff | hist) . . (+7,550) . . N Black box, empty box, and unknown box (Created page with "In Verific Netlist Database, a Netlist can be a black box, an empty box, or an unknown box. #An unknown box is a Netlist that is #*from an instantiation of an undefined Veril...")
- 14:07, 4 June 2020 (diff | hist) . . (+98) . . Main Page
- 17:47, 2 June 2020 (diff | hist) . . (+2,399) . . Message handling
- 17:29, 2 June 2020 (diff | hist) . . (+40) . . Main Page
- 14:12, 1 June 2020 (diff | hist) . . (+1,657) . . N Parsing from data in memory (Created page with "It is possible to use "stream input" to parse data in memory. The example below is For Verilog input, but it can be adapted to use for VHLD input as well. If you run this ap...") (current)
- 14:07, 1 June 2020 (diff | hist) . . (+82) . . Main Page
- 14:44, 14 May 2020 (diff | hist) . . (+49) . . How to use RegisterCallBackMsg() (current)
- 13:30, 14 May 2020 (diff | hist) . . (+3,157) . . N How to use RegisterCallBackMsg() (Created page with "Here is a small example showing how to use RegisterCallBackMsg(): <nowiki> #include <stdio.h> #include <stdarg.h> #include "Strings.h" #include "Map.h" // Make assoc...")
- 13:25, 14 May 2020 (diff | hist) . . (+84) . . Main Page
- 15:19, 13 May 2020 (diff | hist) . . (-10) . . Main Page
- 15:18, 13 May 2020 (diff | hist) . . (+10) . . Main Page
- 20:05, 8 May 2020 (diff | hist) . . (+1) . . System attributes
- 20:03, 8 May 2020 (diff | hist) . . (+12) . . System attributes
- 13:40, 6 May 2020 (diff | hist) . . (+2) . . What VeriModule* or VhdlPrimaryUnit* the Netlist comes from? (current)
- 13:40, 6 May 2020 (diff | hist) . . (+19) . . What VeriModule* or VhdlPrimaryUnit* the Netlist comes from?
- 13:03, 6 May 2020 (diff | hist) . . (+1) . . Macro Callback example (current)
- 13:12, 28 April 2020 (diff | hist) . . (-2) . . How to get best support from Verific
- 13:11, 28 April 2020 (diff | hist) . . (+318) . . How to get best support from Verific
- 11:09, 28 April 2020 (diff | hist) . . (-4) . . How to get best support from Verific
- 12:06, 26 March 2020 (diff | hist) . . (+39) . . Does Verific support XMR?
- 19:03, 14 February 2020 (diff | hist) . . (+30) . . System attributes
- 12:36, 14 February 2020 (diff | hist) . . (-4) . . System attributes
- 12:35, 14 February 2020 (diff | hist) . . (+2) . . System attributes
- 12:33, 14 February 2020 (diff | hist) . . (+323) . . System attributes
- 12:08, 14 February 2020 (diff | hist) . . (+4) . . System attributes
- 12:07, 14 February 2020 (diff | hist) . . (+2) . . System attributes
- 15:20, 13 February 2020 (diff | hist) . . (+46) . . System attributes
- 14:42, 13 February 2020 (diff | hist) . . (-1) . . System attributes
- 14:42, 13 February 2020 (diff | hist) . . (-40) . . System attributes
- 14:41, 13 February 2020 (diff | hist) . . (+2,540) . . N System attributes (Created page with "Verific system attributes are attributes added and attached to DesignObjs (Design Objects) during the process of building the Netlist Database. To distinguish with user-decla...")
- 14:27, 13 February 2020 (diff | hist) . . (+62) . . Main Page
- 17:04, 12 February 2020 (diff | hist) . . (+2,764) . . N Using stream input to ignore input file (Created page with "This example shows how to use stream input to ignore input files that meet certain conditions. The example uses only filename as the "ignore" category. But you can have other...") (current)
- 16:59, 12 February 2020 (diff | hist) . . (+101) . . Main Page
- 16:02, 10 February 2020 (diff | hist) . . (+9,156) . . N Bit-blasting a multi-port RAM instance (Created page with "'''Q: What is bit-blasting a multi-port RAM instance''' Verific’s RAM extraction creates a minimal-port, multi-port RAM model in the netlist for every identifier that behav...") (current)
- 15:55, 10 February 2020 (diff | hist) . . (+103) . . Main Page
- 18:30, 3 February 2020 (diff | hist) . . (+8) . . Main Page
- 17:53, 31 January 2020 (diff | hist) . . (+4,658) . . Memory elements of a RamNet (current)
- 14:00, 29 January 2020 (diff | hist) . . (+21) . . How to check for errors in analysis/elaboration (current)
- 13:13, 29 January 2020 (diff | hist) . . (0) . . How to check for errors in analysis/elaboration
- 13:12, 29 January 2020 (diff | hist) . . (+69) . . How to check for errors in analysis/elaboration
- 13:07, 29 January 2020 (diff | hist) . . (+257) . . How to check for errors in analysis/elaboration
- 18:27, 22 January 2020 (diff | hist) . . (+1) . . Main Page
- 18:25, 22 January 2020 (diff | hist) . . (+4,836) . . N Type Range example with multi-dimensional arrays (Created page with "For a design with multidimensional arrays, the application needs to create a data structure for mapping NetBus to TypeRange. C++: <nowiki> #include <iostream> #include "veri...")
- 18:21, 22 January 2020 (diff | hist) . . (+127) . . Main Page
- 18:06, 22 January 2020 (diff | hist) . . (+3,406) . . N Memory elements of a RamNet (Created page with "In Verific Netlist Database, a RamNet is created for every identifier in the parsetree that is inferred as multi-port memory. This example checks what memory elements are con...")
- 18:02, 22 January 2020 (diff | hist) . . (+78) . . Main Page
- 17:04, 22 January 2020 (diff | hist) . . (+17) . . Main Page
- 17:53, 21 January 2020 (diff | hist) . . (+1) . . How to tell if a module has encrypted contents
- 17:53, 21 January 2020 (diff | hist) . . (+6,736) . . N How to tell if a module has encrypted contents (Created page with "C++ <nowiki> #include <cstring> // for memset #include "veri_file.h" // Make verilog reader available #include "VeriModule.h" // Definition of a VeriModule...")
- 17:50, 21 January 2020 (diff | hist) . . (+115) . . Main Page
- 17:30, 21 January 2020 (diff | hist) . . (+6) . . How to get best support from Verific
- 16:02, 21 January 2020 (diff | hist) . . (0) . . Visiting Hierarchical References (VeriSelectedName)
- 16:02, 21 January 2020 (diff | hist) . . (+6) . . Visiting Hierarchical References (VeriSelectedName)
- 15:59, 21 January 2020 (diff | hist) . . (+3,014) . . N Visiting Hierarchical References (VeriSelectedName) (Created page with "In Verilog parsetree, hierarchical references are of type VeriSelectedName. Note that the "_suffix_id" fields are resolved only in statically-elaborated parsetree. In other wo...")
- 15:54, 21 January 2020 (diff | hist) . . (+2) . . Main Page
- 15:52, 21 January 2020 (diff | hist) . . (+124) . . Main Page
- 17:58, 22 October 2019 (diff | hist) . . (0) . . How to get all Verilog files being analyzed
- 14:55, 4 October 2019 (diff | hist) . . (+2,118) . . N How to ignore a (not used) parameter/generic in elaboration. (Created page with "'''Q: How do I specify the elaborator to ignore parameter/generic that is not used?''' In RTL or static elaboration, parameterized instances are uniquified. For example, this...") (current)
- 14:37, 4 October 2019 (diff | hist) . . (+144) . . Main Page
- 14:11, 21 August 2019 (diff | hist) . . (+2,642) . . N Getting instances' parameters (Created page with "C++: <nowiki> #include "Map.h" #include "Array.h" #include "veri_file.h" #include "VeriModule.h" #include "VeriExpression.h" #include "VeriId.h" #include "VeriScope.h" #ifd...") (current)
- 14:07, 21 August 2019 (diff | hist) . . (+81) . . Main Page
- 12:21, 14 August 2019 (diff | hist) . . (-27) . . Comment out a line using test-based design modification and parsetree modification (current)
- 13:02, 30 July 2019 (diff | hist) . . (+629) . . Prettyprint all modules in the design hierarchy
- 17:10, 29 July 2019 (diff | hist) . . (-23) . . Prettyprint all modules in the design hierarchy
- 17:08, 29 July 2019 (diff | hist) . . (-1,484) . . Prettyprint all modules in the design hierarchy
- 23:29, 28 July 2019 (diff | hist) . . (-1) . . Prettyprint all modules in the design hierarchy
- 23:28, 28 July 2019 (diff | hist) . . (0) . . Prettyprint all modules in the design hierarchy
- 23:26, 28 July 2019 (diff | hist) . . (-2) . . Prettyprint all modules in the design hierarchy
- 23:25, 28 July 2019 (diff | hist) . . (-14) . . Prettyprint all modules in the design hierarchy
- 23:24, 28 July 2019 (diff | hist) . . (+12) . . Prettyprint all modules in the design hierarchy
- 23:22, 28 July 2019 (diff | hist) . . (+7,879) . . N Prettyprint all modules in the design hierarchy (Created page with "There is an API to prettyprint a module, and there is an API to prettyprint all modules in a library. But there is no single API to prettyprint all modules in the design hier...")
- 23:16, 28 July 2019 (diff | hist) . . (+117) . . Main Page
- 16:19, 22 July 2019 (diff | hist) . . (+9) . . Logic optimization across hierarchy boundaries (current)
- 16:19, 22 July 2019 (diff | hist) . . (+9) . . Logic optimization across hierarchy boundaries
- 16:17, 22 July 2019 (diff | hist) . . (+1,446) . . N Logic optimization across hierarchy boundaries (Created page with "Does Verific support design optimizations such as constant propagation and dead-code elimination across hierarchies? The optimization done during elaboration flow in Verific...")
- 16:15, 22 July 2019 (diff | hist) . . (+142) . . Main Page
- 15:30, 22 July 2019 (diff | hist) . . (+5,335) . . N Comment out a line using test-based design modification and parsetree modification (Created page with "C++: <nowiki> #include <iostream> #include "veri_file.h" #include "VeriModule.h" #include "VeriStatement.h" #include "Array.h" #include "Strings.h" #include "TextBasedDes...")
- 15:29, 22 July 2019 (diff | hist) . . (+104) . . Main Page
- 15:20, 16 July 2019 (diff | hist) . . (+2,194) . . N How to get best support from Verific (Created page with "We here at Verific strive try to provide you with the best customer service. But we need help from you. Please: * Identify your company and your group/business unit. Many of...")
- 15:16, 16 July 2019 (diff | hist) . . (+24) . . Main Page
- 18:14, 4 July 2019 (diff | hist) . . (-2) . . How to make lives easier (current)
- 18:13, 4 July 2019 (diff | hist) . . (+374) . . How to make lives easier
- 17:57, 4 July 2019 (diff | hist) . . (-14) . . How to make lives easier
- 17:57, 4 July 2019 (diff | hist) . . (+10) . . Main Page
- 17:55, 4 July 2019 (diff | hist) . . (+2,450) . . N How to make lives easier (Created page with "We here at Verific strive try to provide you with the best customer service. But we need help from you. Together, we'll make our lives easier. So we request you: * Identify...")
- 17:45, 4 July 2019 (diff | hist) . . (+58) . . Main Page
- 16:21, 4 July 2019 (diff | hist) . . (-5) . . How to get packed dimensions of enum
- 16:20, 4 July 2019 (diff | hist) . . (+5,511) . . N How to get packed dimensions of enum (Created page with "C++: <nowiki> #include "Map.h" // Make associated hash table class Map available #include "Set.h" // Make associated hash table class Set available #include "...")
- 16:16, 4 July 2019 (diff | hist) . . (+101) . . Main Page
- 21:19, 11 June 2019 (diff | hist) . . (+171) . . How to get all Verilog files being analyzed
- 18:01, 11 June 2019 (diff | hist) . . (-7) . . How to get all Verilog files being analyzed
- 12:53, 31 May 2019 (diff | hist) . . (+2,000) . . N Static elaboration (Created page with "'''Q: What does 'static elaboration' do?''' Static elaboration runs after analysis. It modifies the parsetree. During static elaboration: * Identify top-level modules and tr...")
- 12:41, 31 May 2019 (diff | hist) . . (+76) . . Main Page
- 16:03, 30 May 2019 (diff | hist) . . (+1,297) . . N Modules/design units with " default" suffix in their names (Created page with "'''Q: After static elaboration, there are modules/design units with "_default" suffix in their names. Why? And what are they? ''' Static elaboration process is a multiple-ite...")
- 15:56, 30 May 2019 (diff | hist) . . (+201) . . Main Page
- 17:25, 9 May 2019 (diff | hist) . . (+30) . . What are the data structures in Verific? (current)
- 17:21, 9 May 2019 (diff | hist) . . (-2) . . What are the data structures in Verific?
- 17:20, 9 May 2019 (diff | hist) . . (-5) . . What are the data structures in Verific?
- 17:19, 9 May 2019 (diff | hist) . . (-42) . . What are the data structures in Verific?
- 17:18, 9 May 2019 (diff | hist) . . (-6) . . What are the data structures in Verific?
- 17:18, 9 May 2019 (diff | hist) . . (-3) . . What are the data structures in Verific?
- 17:17, 9 May 2019 (diff | hist) . . (+1) . . What are the data structures in Verific?
- 17:17, 9 May 2019 (diff | hist) . . (+3) . . What are the data structures in Verific?
- 17:16, 9 May 2019 (diff | hist) . . (-9) . . What are the data structures in Verific?
- 17:15, 9 May 2019 (diff | hist) . . (+3) . . What are the data structures in Verific?
- 17:15, 9 May 2019 (diff | hist) . . (+11) . . What are the data structures in Verific?
- 17:14, 9 May 2019 (diff | hist) . . (+82) . . What are the data structures in Verific?
- 17:11, 9 May 2019 (diff | hist) . . (-2) . . What are the data structures in Verific?
- 17:09, 9 May 2019 (diff | hist) . . (0) . . What are the data structures in Verific?
- 17:08, 9 May 2019 (diff | hist) . . (-1) . . What are the data structures in Verific?
- 12:03, 9 April 2019 (diff | hist) . . (+1,414) . . Retrieve package name for user-defined variable types (current)
- 12:02, 9 April 2019 (diff | hist) . . (0) . . Main Page
- 12:01, 9 April 2019 (diff | hist) . . (+7) . . Main Page
- 12:41, 3 April 2019 (diff | hist) . . (+787) . . Access attributes of ports in parsetree
- 12:39, 3 April 2019 (diff | hist) . . (+1,864) . . N Access attributes of ports in parsetree (Created page with " <nowiki> #!/usr/bin/perl use strict ; push(@INC, "../pm") ; require "Verific.pm" ; if (!Verific::veri_file::Read("test.v")) { exit 1 ; } my $mod = Verific::veri_file::Get...")
- 12:38, 3 April 2019 (diff | hist) . . (+102) . . Main Page
- 15:20, 7 March 2019 (diff | hist) . . (+3) . . Main Page
- 15:20, 7 March 2019 (diff | hist) . . (+28) . . Main Page
- 16:56, 4 March 2019 (diff | hist) . . (-2) . . Verific data structures
- 16:55, 4 March 2019 (diff | hist) . . (+49) . . Verific data structures
- 16:48, 4 March 2019 (diff | hist) . . (+2,846) . . N Statically elaborate with different values of parameters (Created page with "C++: <nowiki> #include "VeriCopy.h" // Make class VeriMapForCopy available #include "Map.h" // Make class Map available #include "Message.h" // Make m...")
- 16:46, 4 March 2019 (diff | hist) . . (+135) . . Main Page
- 16:25, 4 March 2019 (diff | hist) . . (+6,710) . . N Traverse instances in parsetree (Created page with "C++: <nowiki> // Verific utilities #include "Array.h" // Make class Array available #include "Set.h" // Make class Set available #include "Message.h"...")
- 16:23, 4 March 2019 (diff | hist) . . (+90) . . Main Page
- 17:17, 1 March 2019 (diff | hist) . . (-1) . . Process -f file and explore the Netlist Database (C++) (current)
- 17:16, 1 March 2019 (diff | hist) . . (+5,263) . . Process -f file and explore the Netlist Database (C++)
- 17:15, 1 March 2019 (diff | hist) . . (+1,579) . . N Process -f file and explore the Netlist Database (C++) (Created page with " <nowiki> #include <iostream> #include <fstream> #include "veri_file.h" #include "VeriModule.h" #include "VeriId.h" #include "VeriScope.h" #include "Set.h" using namespace...")
- 17:14, 1 March 2019 (diff | hist) . . (0) . . Process -f file and explore the Netlist Database (py) (current)
- 17:13, 1 March 2019 (diff | hist) . . (+5) . . Main Page
(newest | oldest) View (newer 250 | older 250) (20 | 50 | 100 | 250 | 500)