Under terms of the agreement, Verific will acquire Invionics Software’s entire INVIO technology portfolio, for electronic design automation (EDA) tools and flows. An R&D group with real-world design experience and a deep understanding of EDA software development will join Verific’s engineering department.
SystemVerilog and VHDL parsers from Verific serve as the front end to Austemper’s software that analyzes, augments and verifies functional safety in system-on-chip (SoC), application specific integrated circuit (ASIC) and intellectual property (IP) designs ensuring they meet functional safety requirements.
New Functionality Broadens UPF Parser/Analyzer Capabilities
Verific Design Automation, the recognized leader of SystemVerilog, VHDL and Unified Power Format (UPF) Parser Platforms in production and development use throughout the semiconductor industry, today announced availability of its UPF Elaborator.
A startup can shave 12 months or more off the development cycle by outsourcing non-essential elements of product design.
I’m hearing from different sources that investments in electronic design automation (EDA) and semiconductor startups are picking up around the globe and not just in Silicon Valley. That’s welcome news –– and long overdue –– as we move through 2017. With funding come new and innovative products and the cycle of growth to acquisition or other successful outcomes endures.
I had an interesting conversation with Michiel Ligthart and Rick Carlson of Verific. They have a unique niche in the EDA ecosystem. They provide parsers for SystemVerilog, VHDL, and IEEE 1801 (fka UPF). They really have no competition other than companies that develop their own parsers in-house, usually for historical reasons.
Michiel Ligthart, President and COO of Verific Design Automation, and Rick Carlson, VP of Worldwide Sales, have a proposal for young companies in the EDA industry and adjacent technologies: Come to Verific if your organization is early stage, in need of encouragement and wise counsel, and could benefit from access to Verific software to help you progress towards a commercial product launch.
Read more at edacafe.com
Verific to Showcase Three Design Automation Startups With Safety-Features Insertion, Low-Power, Hardware Security Analysis Offerings in Its DAC Booth
Read more at finance.yahoo.com
Robert Gardner, longtime member of the Verific Design Automation Board of Directors, will be presented with the yearly DATE Fellow Award by the Design, Automation and Test in Europe (DATE) Conference and Exhibit 2016.
He will receive the prestigious award in recognition of his long association and support of DATE during the Opening Ceremonies March 15.
Read more at finance.yahooc.om
The new UPF 3.0 standard offers additional enhancements to address and describe power intent of complex systems on chip (SoCs).
Read more at eetimes.com