A few days ago, Menta of Montpellier, France, announced that it had selected IEEE-compliant Verilog, SystemVerilog, and VHDL parsers from Verific to serve as the front-end to Menta’s Origami Designer and Origami Programmer tools used to create embedded FPGAs for SoC designs.

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Electronic Design Automation (EDA) component software leaders Concept Engineering and Verific Design Automation today announced immediate availability of a connectivity package that links Concept Engineering’s Nlview^TM schematic generator and visualization engine with Verific’s netlist database.

VVDI-Link gives Nlview, used within EDA tools to automatically create and visualize schematics for different levels of electronic circuits, direct access to the Verific database of industry-standard, IEEE-compliant SystemVerilog and VHDL parsers. It is available from Concept Engineering as part of its Nlview family at no additional charge to existing customers.

“Concept Engineering and Verific have worked together since 2003 and continue to look for ways that will improve a designer’s productivity,” says Michiel Ligthart, Verific’s president and chief operating officer. “While a connectivity package may seem trivial, it’s actually a critical link.”

The same technology is deployed in Concept Engineering’s RTLvision® PRO tool, a powerful, easy-to-use register transfer level (RTL) viewer and debugger that combines Verilog, VHDL and SystemVerilog viewers in one integrated debugging cockpit.

“Software design teams rely on high-quality software components, such as automatic schematic generators and language parsers, which is why it was important to link our tools together,” comments Gerhard Angst, Concept Engineering’s chief executive officer and president. “Our new VVDI-Link package makes it easy to create innovative debugging cockpits for EDA tools.”

Concept Engineering’s Nlview provides automatic generation of schematic diagrams for different levels of electronic circuits, including transistor, gate, RTL, block and system. A fine granularity of user preferences can be mixed with machine computed “beauty” for the best human-readable diagrams. Interactive circuit exploration is supported by incremental schematic generation and navigation technology. Nlview provides a set of application programming interfaces (APIs) and interfaces for different GUI platforms.

Verific’s software is the front end to a variety of EDA and field programmable gate array (FPGA) tools for analysis, simulation, verification, synthesis, emulation and test of RTL designs. Its Parser Platform includes support for SystemVerilog, Verilog, VHDL and UPF, and provides C++ and Perl APIs. Verific’s software is distributed as C++ source code and compiles on all 32- and 64-bit Unix, Linux and Windows operating systems.

Verific Design Automation, supplier of industry-standard, IEEE-compliant SystemVerilog and VHDL parsers, today announced enhancements to its parser forthe IEEE 1801-2013standard for the design and verification of low-power integrated circuits, also known as Universal Power Format 2.1 (UPF 2.1).

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Verific Design Automation, provider of SystemVerilog, Verilog and VHDL parsers, closed 2013 with a double-digit increase in revenue and56 active user companies, many of whom are longstanding customers.

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Verific Design Automation, provider of SystemVerilog, Verilog and VHDL parsers, today announced that Tabula (www.tabula.com) has added Verific’s SystemVerilog parser as front-end support to version 2.7.1 of its Stylus® compiler.

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Verific Design Automation, provider of SystemVerilog, Verilog and VHDL parsers, ended 2012 with 52 active user companies and a revenue increase of 20% over 2011.

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Verific Design Automation today announced it licensed its industry-standard, IEEE-compliant SystemVerilog and VHDL platform to Aldec, Inc.,a global leader in electronic design verification, to be included into its Hardware Emulation Solution (HES™).

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Excellicon, a first-time exhibitor of end-to-end Timing Constraints Solution at the Design Automation Conference (DAC), today announced it adopted Verific Design Automation’s industry-standard, IEEE-compliant front-end platform for use with its software for timing constraints authoring, verification and management.

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Verific Design Automation, supplier of industry-standard, IEEE-compliant SystemVerilog and VHDL front-end solutions, has been selected by Blue Pearl Software to support its Blue Pearl Software Suite.

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Verific Design Automation today announced immediate availability of a parser for the IEEE 1801-2009 Standard for Design and Verification of Low-Power Integrated Circuits. Also known as Unified Power Format 2.0 (UPF 2.0), it was developed by standards organization Accellera and carries the support of multiple EDA vendors.

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