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25 August 2011

vSync Circuits licenses Verific’s Parser Platform

Verific Design Automation, supplier of industry-standard, IEEE-compliant hardware description language (HDL) front-end solutions, today announced vSync Circuits Ltd.   in Israel has licensed its parser platform for use with the vSync clock domain crossing (CDC) verification software.

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Filed Under: Geen categorie

20 May 2011

Verific unveils Perl interface for its SystemVerilog and VHDL front-end solutions

The folks at Verific Design Automation, long known for their SystemVerilog and VHDL front-end solutions used by leading EDA, FPGA and semiconductor companies worldwide, have just unveiled a Perl interface to their industry-standard, IEEE-compliant SystemVerilog and VHDL parsers and elaborators.

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Filed Under: Geen categorie

4 April 2011

Ausdia Licenses Verific’s Parser Platform

Ausdia Inc., provider of chip design and closure solutions, has licensed Verific Design Automation’s Verilog parser platform for use with its analysis and optimization software for accelerating timing constraint development, constraint validation and timing closure.”When we looked for a platform for RTL analysis, we quickly realized that the only answer was Verific,” says Sam Appleton, Ausdia’s chief executive officer (CEO).

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Filed Under: Geen categorie

20 January 2011

Nextop selects Verific’s SystemVerilog front end

Verific Design Automation today said that NextOp Software, Inc. has licensed its software for use with the NextOp assertion-based verification solutions that allow design and verification teams to uncover bugs, expose functional coverage holes, and increase verification observability.

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Filed Under: Geen categorie

6 November 2010

Veridae licenses Verific for Clarus family of debug products

Verific Design Automation and Veridae Systems jointly announced today that the Verific front-end software has been licensed to Veridae for inclusion in the new Clarus family of debug and validation products.Verific’s Verilog analyzer and static elaborator is a platform for parsing the IEEE Verilog standard, allowing Clarus to work with a comprehensive internal representation of a register transfer level (RTL) design rather than the original Verilog language.

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Filed Under: Geen categorie

20 October 2010

Verific Joins Cadence Connections Program

Verific Design Automation, supplier of de facto standard SystemVerilog and VHDL front-end software to the electronic design automation (EDA) and semiconductor community, announced today that it has become a member of the Cadence Design Systems Connections® program.

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Filed Under: Geen categorie

22 April 2010

Forte renews license for Verific Software

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Filed Under: Geen categorie

31 March 2010

Parallel Engines Licenses Verific Design Automation Software

Verific Design Automation, supplier of de facto standard front-end software, today announced newly launched Parallel Engines Corporation has integrated its software into a toolset that merges semiconductor intellectual property (IP) and Electronic Design Automation (EDA) into one system.

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Filed Under: Geen categorie

17 February 2010

Vennsa Picks Verific’s de facto Front End Software

Vennsa Technologies Inc., the leader in automated debugging and error localization software, today announced that de facto standard front-end software from Verific Design Automation serves as the front end for OnPoint™, its breakthrough tool in automated debugging.

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Filed Under: Geen categorie

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