Verific’s SystemVerilog parser supports the entire IEEE-1800 standard (2017, 2012, 2009, 2005) and includes regular Verilog (IEEE 1164).
- The parser is compatible with leading industry simulators Xcelium, QuestaSim, and VCS.
- The parser supports static elaboration as well as RTL elaboration, and is integrated with a language-independent netlist data structure common to all parsers.
- RTL elaboration supports all synthesis pragma’s and is compatible with leading synthesis tools such as Design Compiler, RTL Compiler, Synplify, and Precision.
- Users interface with the parse tree or netlist data structures through an extensive set of APIs in C++, Perl, or Python.
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