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1. A customer wants to analyze/elaborate
2. Access attributes in parsetree
3. Access attributes of ports in parsetree
4. Accessing and evaluating module's parameters
5. Bit-blasting a multi-port RAM instance
6. Black box, empty box, and unknown box
7. Buffering signals and ungrouping
8. Comment out a line using test-based design modification and parsetree modification
9. Comment out a line using text based design modification and parsetree modification
10. Compile-time/run-time flags
11. Constant expression replacement
12. Create DOT diagram of parse tree
13. Create a Netlist Database from scratch (not from RTL elaboration)
14. Cross-reference between the original RTL files and the elaborated netlist
15. Defined macros become undefined - MFCU vs SFCU
16. Design with System Verilog and Verilog 2001 files
17. Design with VHDL-1993 and VHDL-2008 files
18. Difference between RTL and gate-level simulations - Flipflop with async set and async reset
19. Does Verific build CDFG?
20. Does Verific support XMR?
21. Does Verific support cross
22. Does Verific support cross module references (XMR)?
23. Escaped identifiers in RTL files and in Verific data structures
24. Evaluate 'for-generate' loop
25. Extract clock enable
26. Fanout cone and grouping
27. Finding hierarchical paths of a Netlist
28. General
29. Getting design hierarchy from input RTL files
30. Getting instances' parameters
31. Hierarchy tree RTL elaboration
32. How Verific elaborator handles blackboxes/unknown boxes
33. How do I know
34. How do I know what language a Netlist in the netlist database comes from?
35. How to change name of id in Verilog parsetree
36. How to check for errors in analysis/elaboration
37. How to create a Netlist database from scratch (not from RTL input)
38. How to create new module in Verilog parsetree
39. How to detect multiple-clock-edge condition in Verilog parsetree
40. How to enable long paths on Windows?
41. How to evaluate a VHDL expression
42. How to evaluate a Verilog expression
43. How to find port dimensions
44. How to get all Verilog files being analyzed
45. How to get best support from Verific
46. How to get driving net of an instance
47. How to get enums from Verilog parsetree
48. How to get full hierarchy ID path
49. How to get library containing nested module
50. How to get linefile data of macros - Macro callback function

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