Geen categorie Archives - Page 7 of 15 - Verific Design Automation

13 January 2020

Celebrating 20 Years of Exceptional Support, Part 1

Fierce Loyalty to Verific’s Value

An interview with Scott Aron Bloom, former chief technology officer at Blue Pearl and a 17-year Verific customer, is perhaps the best way to kick-off the blog post series. “I’m fiercely loyal and value what Verific provides.”

13 January 2020

Celebrating 20 Years of Exceptional Support

Six Short Interviews with Some of Verific’s Long-Time Customers Highlight Positive Experience

Nanette Collins, public relations consultant for Verific, interviewed several of Verific’s long-time customers and wrote a six-part blog series on their experience with Verific.

3 December 2019

vSync Circuits Adds Verific’s Static Elaborator to Product Mix

Verific Design Automation today announced long-time customer vSync Circuits added Verific’s static elaboration to its product mix and introduced vLinter, early rule-based design analysis and verification software.

29 May 2019

Verific, 20 Years Terrific

What do JasperGold, Stratus, and the Rocketick part of Xcelium have in common? Well, they are all Cadence products, of course. But they also all use Verific as parsers for SystemVerilog, Verilog, and VHDL.

Verific got started twenty years ago, Rob Dekker told me.

26 April 2019

Foundational Excellence in a Laid-Back Style

I recently had a call with Rob Dekker, Founder and CTO of Verific. If you’re in EDA or semiconductor CAD, chances are high that you know who they are. They’re king of the hill in parser software for SystemVerilog and VHDL.