The folks at Verific Design Automation, long known for their SystemVerilog and VHDL front-end solutions used by leading EDA, FPGA and semiconductor companies worldwide, have just unveiled a Perl interface to their industry-standard, IEEE-compliant SystemVerilog and VHDL parsers and elaborators.
Ausdia Inc., provider of chip design and closure solutions, has licensed Verific Design Automation’s Verilog parser platform for use with its analysis and optimization software for accelerating timing constraint development, constraint validation and timing closure.”When we looked for a platform for RTL analysis, we quickly realized that the only answer was Verific,” says Sam Appleton, Ausdia’s chief executive officer (CEO).
Verific Design Automation today said that NextOp Software, Inc. has licensed its software for use with the NextOp assertion-based verification solutions that allow design and verification teams to uncover bugs, expose functional coverage holes, and increase verification observability.
Verific Design Automation and Veridae Systems jointly announced today that the Verific front-end software has been licensed to Veridae for inclusion in the new Clarus family of debug and validation products.Verific’s Verilog analyzer and static elaborator is a platform for parsing the IEEE Verilog standard, allowing Clarus to work with a comprehensive internal representation of a register transfer level (RTL) design rather than the original Verilog language.
Verific Design Automation, supplier of de facto standard SystemVerilog and VHDL front-end software to the electronic design automation (EDA) and semiconductor community, announced today that it has become a member of the Cadence Design Systems Connections® program.