I recently had a call with Rob Dekker, Founder and CTO of Verific. If you’re in EDA or semiconductor CAD, chances are high that you know who they are. They’re king of the hill in parser software for SystemVerilog and VHDL.

Read more at SemiWiki.com.

Sanjay Gangal interviewed Michiel Ligthart, President and COO at Verific Design Automation at the 2019 DVCon.

Watch the video at EDAcafe.com.

Verific Design Automation today announced Innergy Systems licensed its Parser Platform to serve as the front end to its new Power Analysis Platform that combines quick-debug power analysis with fast power model generation.

Read more at EDACafe.com.

Verific Design Automation today announced Empyrean, provider of fast and physically aware, design closure and optimization solutions for systems on chip (SoCs), licensed its Parser Platform to function as the front end to Qualib, library quality inspection software.

Read more at EDACafe.com.

Verific today announced full integration of INVIO with its flagship parser platforms. This follows an earlier announcement that it acquired from Invionics Software the INVIO platform, with its high-level level application programming interfaces (APIs) that enable Verific users to simplify and streamline their design environment, accelerating tool development.

Read more at EDACafe.com.