Difference between revisions of "Main Page"
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* [[Original RTL language | How do I know what language a Netlist in the netlist database comes from?]] | * [[Original RTL language | How do I know what language a Netlist in the netlist database comes from?]] | ||
* [[Verific data structures | What are the data structures in Verific?]] | * [[Verific data structures | What are the data structures in Verific?]] | ||
+ | * [[Remove Verific data structures | How do I remove all Verific data structures in memory?]] | ||
* [[Does Verific build CDFG? | Does Verific build control and data flow graph (CDFG)?]] | * [[Does Verific build CDFG? | Does Verific build control and data flow graph (CDFG)?]] | ||
* [[Does Verific support XMR?| Does Verific support cross module references (XMR)?]] | * [[Does Verific support XMR?| Does Verific support cross module references (XMR)?]] | ||
+ | * [[Compile-time/run-time flags | Are there options to control Verific software's behavior?]] | ||
+ | * [[Message handling | How do I downgrade/upgrade messages from Verific? ]] | ||
+ | * [[Release version | How do I tell the version of a Verific software release? ]] | ||
+ | * [[Tcl library path| How to correct building (linking) issue "/usr/bin/ld: cannot find -ltcl"]] | ||
− | '''VHDL, Verilog, Liberty, EDIF''' | + | '''Input: VHDL, Verilog (and SystemVerilog), Liberty, EDIF''' |
− | * [[How to get all Verilog files being analyzed | I'm using -v, -y, .... After Verific is done with the analysis, how do I get a list of all the files being analyzed?]] | + | * [[How to get all Verilog files being analyzed | Verilog: I'm using -v, -y, .... After Verific is done with the analysis, how do I get a list of all the files being analyzed?]] |
− | * [[ | + | * [[Included files associated with a Verilog source file | Verilog: How do I get the list of included files associated with a Verilog source file?]] |
− | * [[Verilog ports being renamed | Why are the ports in original Verilog file renamed to p1, p2, ....?]] | + | * [[Prettyprint to a string | Verilog: How to prettyprint a parsetree node to a string.]] |
− | * [[Design with System Verilog and Verilog 2001 files | For a design consisting of a mixture of Verilog 2001 and SystemVerilog input files, should I parse all the files as SystemVerilog?]] | + | * [[How to get type/initial value of parameters | Verilog: How to get type/initial value of parameters.]] |
− | * [[Design with VHDL-1993 and VHDL-2008 files | VHDL-1993 and VHDL-2008 each has its own IEEE library set. How do I analyze/elaborate a design with a mixture of files of different VHDL dialects (1993 and 2008)?]] | + | * [[Verilog ports being renamed | Verilog: Why are the ports in original Verilog file renamed to p1, p2, ....?]] |
− | * [[ | + | * [[Design with System Verilog and Verilog 2001 files | Verilog: For a design consisting of a mixture of Verilog 2001 and SystemVerilog input files, should I parse all the files as SystemVerilog?]] |
+ | * [[How to get module ports from Verilog parsetree | Verilog: From the Verilog parsetree, how can I get the ports of a module?]] | ||
+ | * [[How to change name of id in Verilog parsetree | Verilog: How do I change the name of an id (VeriidDef) in Verilog parsetree?]] | ||
+ | * [[How to get library containing nested module | Verilog: How do I get the library that contains the module nested inside another module?]] | ||
+ | * [[How to get linefile information of macro definitions | Verilog: How do I get linefile information of macro definitions?]] | ||
+ | * [[How to find port dimensions | Verilog: How do I get port dimensions?]] | ||
+ | * [[Instance - Module binding order | Verilog: What is the order of binding modules to instances?]] | ||
+ | * [[Constant expression replacement | Verilog: Does Verific replace constant expressions with their respective values?]] | ||
+ | * [[Defined macros become undefined - MFCU vs SFCU | SystemVerilog: Why does Verific complain about undefined macros for macros defined in a different file?]] | ||
+ | * [[How to get enums from Verilog parsetree | SystemVerilog: From the parsetree, how can I get the enums declared in a module?]] | ||
+ | * [[How to identify packages being imported into a module | SystemVerilog: How do I identify packages being imported into a module?]] | ||
+ | * [[SystemVerilog "std" package | SystemVerilog: Support for SystemVerilog semaphore/process/mailbox constructs.]] | ||
+ | * [[Top level module with interface ports | SystemVerilog: Support for SystemVerilog top level module with interface ports.]] | ||
+ | * [[Design with VHDL-1993 and VHDL-2008 files | VHDL: VHDL-1993 and VHDL-2008 each has its own IEEE library set. How do I analyze/elaborate a design with a mixture of files of different VHDL dialects (1993 and 2008)?]] | ||
+ | * [[What VeriModule* or VhdlPrimaryUnit* the Netlist comes from? | Verilog/VHDL: For a Netlist in the netlist database, is there a clean way to look back at what VeriModule* or VhdlPrimaryUnit* the Netlist was derived from?]] | ||
+ | * [[How to ignore parameters/generics in elaboration | Verilog/VHDL: Is there a way to tell the elaborator to ignore certain parameters/generics so that the unit/module is not uniquified?]] | ||
+ | * [[How to check for errors in analysis/elaboration | Verilog/VHDL: Is there a way to tell if the analysis/elaboration process has errors?]] | ||
+ | * [[Support IEEE 1735 encryption standard | Verilog/VHDL: Does Verific support IEEE 1735 encryption standard?]] | ||
+ | '''Netlist Database''' | ||
+ | * [[How to create a Netlist database from scratch (not from RTL input) | A coding example as how to create Netlist database and its objects]] | ||
'''Output''' | '''Output''' | ||
− | * [[Output file formats | What | + | * [[Output file formats | What language formats does Verific support as output?]] |
'''TCL, Perl, Python, Java''' | '''TCL, Perl, Python, Java''' | ||
* [[What languages can I use with Verific software? | What programming languages can I use with Verific software?]] | * [[What languages can I use with Verific software? | What programming languages can I use with Verific software?]] |
Revision as of 17:13, 28 December 2018
General
- How do I know what language a Netlist in the netlist database comes from?
- What are the data structures in Verific?
- How do I remove all Verific data structures in memory?
- Does Verific build control and data flow graph (CDFG)?
- Does Verific support cross module references (XMR)?
- Are there options to control Verific software's behavior?
- How do I downgrade/upgrade messages from Verific?
- How do I tell the version of a Verific software release?
- How to correct building (linking) issue "/usr/bin/ld: cannot find -ltcl"
Input: VHDL, Verilog (and SystemVerilog), Liberty, EDIF
- Verilog: I'm using -v, -y, .... After Verific is done with the analysis, how do I get a list of all the files being analyzed?
- Verilog: How do I get the list of included files associated with a Verilog source file?
- Verilog: How to prettyprint a parsetree node to a string.
- Verilog: How to get type/initial value of parameters.
- Verilog: Why are the ports in original Verilog file renamed to p1, p2, ....?
- Verilog: For a design consisting of a mixture of Verilog 2001 and SystemVerilog input files, should I parse all the files as SystemVerilog?
- Verilog: From the Verilog parsetree, how can I get the ports of a module?
- Verilog: How do I change the name of an id (VeriidDef) in Verilog parsetree?
- Verilog: How do I get the library that contains the module nested inside another module?
- Verilog: How do I get linefile information of macro definitions?
- Verilog: How do I get port dimensions?
- Verilog: What is the order of binding modules to instances?
- Verilog: Does Verific replace constant expressions with their respective values?
- SystemVerilog: Why does Verific complain about undefined macros for macros defined in a different file?
- SystemVerilog: From the parsetree, how can I get the enums declared in a module?
- SystemVerilog: How do I identify packages being imported into a module?
- SystemVerilog: Support for SystemVerilog semaphore/process/mailbox constructs.
- SystemVerilog: Support for SystemVerilog top level module with interface ports.
- VHDL: VHDL-1993 and VHDL-2008 each has its own IEEE library set. How do I analyze/elaborate a design with a mixture of files of different VHDL dialects (1993 and 2008)?
- Verilog/VHDL: For a Netlist in the netlist database, is there a clean way to look back at what VeriModule* or VhdlPrimaryUnit* the Netlist was derived from?
- Verilog/VHDL: Is there a way to tell the elaborator to ignore certain parameters/generics so that the unit/module is not uniquified?
- Verilog/VHDL: Is there a way to tell if the analysis/elaboration process has errors?
- Verilog/VHDL: Does Verific support IEEE 1735 encryption standard?
Netlist Database
Output
TCL, Perl, Python, Java