Difference between revisions of "Main Page"

From Verific Design Automation FAQ
Jump to: navigation, search
Line 60: Line 60:
 
* [[Type Range example | Verilog/C++: Type Range Example]]
 
* [[Type Range example | Verilog/C++: Type Range Example]]
 
* [[Macro Callback example | Verilog/C++: Macro Callback example]]
 
* [[Macro Callback example | Verilog/C++: Macro Callback example]]
 +
* [[How to tell if a module has encrypted contents | Verilog/C++: How to tell if a module has encrypted contents]]
 
* [[Comment out a line using test-based design modification and parsetree modification | Verilog/C++: Comment out a line using test-based design modification and parsetree modification]]  
 
* [[Comment out a line using test-based design modification and parsetree modification | Verilog/C++: Comment out a line using test-based design modification and parsetree modification]]  
 
* [[Access attributes of ports in parsetree | Verilog/Perl: Access attributes of ports in parsetree]]
 
* [[Access attributes of ports in parsetree | Verilog/Perl: Access attributes of ports in parsetree]]

Revision as of 17:50, 21 January 2020

General

Input: VHDL, Verilog (and SystemVerilog), Liberty, EDIF

Netlist Database

Output

Scripting languages: TCL, Perl, Python

Code examples