User contributions
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- 17:04, 12 February 2020 (diff | hist) . . (+2,764) . . N Using stream input to ignore input file (Created page with "This example shows how to use stream input to ignore input files that meet certain conditions. The example uses only filename as the "ignore" category. But you can have other...") (current)
- 16:59, 12 February 2020 (diff | hist) . . (+101) . . Main Page
- 16:02, 10 February 2020 (diff | hist) . . (+9,156) . . N Bit-blasting a multi-port RAM instance (Created page with "'''Q: What is bit-blasting a multi-port RAM instance''' Verific’s RAM extraction creates a minimal-port, multi-port RAM model in the netlist for every identifier that behav...") (current)
- 15:55, 10 February 2020 (diff | hist) . . (+103) . . Main Page
- 18:30, 3 February 2020 (diff | hist) . . (+8) . . Main Page
- 17:53, 31 January 2020 (diff | hist) . . (+4,658) . . Memory elements of a RamNet (current)
- 14:00, 29 January 2020 (diff | hist) . . (+21) . . How to check for errors in analysis/elaboration (current)
- 13:13, 29 January 2020 (diff | hist) . . (0) . . How to check for errors in analysis/elaboration
- 13:12, 29 January 2020 (diff | hist) . . (+69) . . How to check for errors in analysis/elaboration
- 13:07, 29 January 2020 (diff | hist) . . (+257) . . How to check for errors in analysis/elaboration
- 18:27, 22 January 2020 (diff | hist) . . (+1) . . Main Page
- 18:25, 22 January 2020 (diff | hist) . . (+4,836) . . N Type Range example with multi-dimensional arrays (Created page with "For a design with multidimensional arrays, the application needs to create a data structure for mapping NetBus to TypeRange. C++: <nowiki> #include <iostream> #include "veri...")
- 18:21, 22 January 2020 (diff | hist) . . (+127) . . Main Page
- 18:06, 22 January 2020 (diff | hist) . . (+3,406) . . N Memory elements of a RamNet (Created page with "In Verific Netlist Database, a RamNet is created for every identifier in the parsetree that is inferred as multi-port memory. This example checks what memory elements are con...")
- 18:02, 22 January 2020 (diff | hist) . . (+78) . . Main Page
- 17:04, 22 January 2020 (diff | hist) . . (+17) . . Main Page
- 17:53, 21 January 2020 (diff | hist) . . (+1) . . How to tell if a module has encrypted contents
- 17:53, 21 January 2020 (diff | hist) . . (+6,736) . . N How to tell if a module has encrypted contents (Created page with "C++ <nowiki> #include <cstring> // for memset #include "veri_file.h" // Make verilog reader available #include "VeriModule.h" // Definition of a VeriModule...")
- 17:50, 21 January 2020 (diff | hist) . . (+115) . . Main Page
- 17:30, 21 January 2020 (diff | hist) . . (+6) . . How to get best support from Verific
- 16:02, 21 January 2020 (diff | hist) . . (0) . . Visiting Hierarchical References (VeriSelectedName)
- 16:02, 21 January 2020 (diff | hist) . . (+6) . . Visiting Hierarchical References (VeriSelectedName)
- 15:59, 21 January 2020 (diff | hist) . . (+3,014) . . N Visiting Hierarchical References (VeriSelectedName) (Created page with "In Verilog parsetree, hierarchical references are of type VeriSelectedName. Note that the "_suffix_id" fields are resolved only in statically-elaborated parsetree. In other wo...")
- 15:54, 21 January 2020 (diff | hist) . . (+2) . . Main Page
- 15:52, 21 January 2020 (diff | hist) . . (+124) . . Main Page
- 17:58, 22 October 2019 (diff | hist) . . (0) . . How to get all Verilog files being analyzed
- 14:55, 4 October 2019 (diff | hist) . . (+2,118) . . N How to ignore a (not used) parameter/generic in elaboration. (Created page with "'''Q: How do I specify the elaborator to ignore parameter/generic that is not used?''' In RTL or static elaboration, parameterized instances are uniquified. For example, this...") (current)
- 14:37, 4 October 2019 (diff | hist) . . (+144) . . Main Page
- 14:11, 21 August 2019 (diff | hist) . . (+2,642) . . N Getting instances' parameters (Created page with "C++: <nowiki> #include "Map.h" #include "Array.h" #include "veri_file.h" #include "VeriModule.h" #include "VeriExpression.h" #include "VeriId.h" #include "VeriScope.h" #ifd...") (current)
- 14:07, 21 August 2019 (diff | hist) . . (+81) . . Main Page
- 12:21, 14 August 2019 (diff | hist) . . (-27) . . Comment out a line using test-based design modification and parsetree modification (current)
- 13:02, 30 July 2019 (diff | hist) . . (+629) . . Prettyprint all modules in the design hierarchy
- 17:10, 29 July 2019 (diff | hist) . . (-23) . . Prettyprint all modules in the design hierarchy
- 17:08, 29 July 2019 (diff | hist) . . (-1,484) . . Prettyprint all modules in the design hierarchy
- 23:29, 28 July 2019 (diff | hist) . . (-1) . . Prettyprint all modules in the design hierarchy
- 23:28, 28 July 2019 (diff | hist) . . (0) . . Prettyprint all modules in the design hierarchy
- 23:26, 28 July 2019 (diff | hist) . . (-2) . . Prettyprint all modules in the design hierarchy
- 23:25, 28 July 2019 (diff | hist) . . (-14) . . Prettyprint all modules in the design hierarchy
- 23:24, 28 July 2019 (diff | hist) . . (+12) . . Prettyprint all modules in the design hierarchy
- 23:22, 28 July 2019 (diff | hist) . . (+7,879) . . N Prettyprint all modules in the design hierarchy (Created page with "There is an API to prettyprint a module, and there is an API to prettyprint all modules in a library. But there is no single API to prettyprint all modules in the design hier...")
- 23:16, 28 July 2019 (diff | hist) . . (+117) . . Main Page
- 16:19, 22 July 2019 (diff | hist) . . (+9) . . Logic optimization across hierarchy boundaries (current)
- 16:19, 22 July 2019 (diff | hist) . . (+9) . . Logic optimization across hierarchy boundaries
- 16:17, 22 July 2019 (diff | hist) . . (+1,446) . . N Logic optimization across hierarchy boundaries (Created page with "Does Verific support design optimizations such as constant propagation and dead-code elimination across hierarchies? The optimization done during elaboration flow in Verific...")
- 16:15, 22 July 2019 (diff | hist) . . (+142) . . Main Page
- 15:30, 22 July 2019 (diff | hist) . . (+5,335) . . N Comment out a line using test-based design modification and parsetree modification (Created page with "C++: <nowiki> #include <iostream> #include "veri_file.h" #include "VeriModule.h" #include "VeriStatement.h" #include "Array.h" #include "Strings.h" #include "TextBasedDes...")
- 15:29, 22 July 2019 (diff | hist) . . (+104) . . Main Page
- 15:20, 16 July 2019 (diff | hist) . . (+2,194) . . N How to get best support from Verific (Created page with "We here at Verific strive try to provide you with the best customer service. But we need help from you. Please: * Identify your company and your group/business unit. Many of...")
- 15:16, 16 July 2019 (diff | hist) . . (+24) . . Main Page
- 18:14, 4 July 2019 (diff | hist) . . (-2) . . How to make lives easier (current)
- 18:13, 4 July 2019 (diff | hist) . . (+374) . . How to make lives easier
- 17:57, 4 July 2019 (diff | hist) . . (-14) . . How to make lives easier
- 17:57, 4 July 2019 (diff | hist) . . (+10) . . Main Page
- 17:55, 4 July 2019 (diff | hist) . . (+2,450) . . N How to make lives easier (Created page with "We here at Verific strive try to provide you with the best customer service. But we need help from you. Together, we'll make our lives easier. So we request you: * Identify...")
- 17:45, 4 July 2019 (diff | hist) . . (+58) . . Main Page
- 16:21, 4 July 2019 (diff | hist) . . (-5) . . How to get packed dimensions of enum
- 16:20, 4 July 2019 (diff | hist) . . (+5,511) . . N How to get packed dimensions of enum (Created page with "C++: <nowiki> #include "Map.h" // Make associated hash table class Map available #include "Set.h" // Make associated hash table class Set available #include "...")
- 16:16, 4 July 2019 (diff | hist) . . (+101) . . Main Page
- 21:19, 11 June 2019 (diff | hist) . . (+171) . . How to get all Verilog files being analyzed
- 18:01, 11 June 2019 (diff | hist) . . (-7) . . How to get all Verilog files being analyzed
- 12:53, 31 May 2019 (diff | hist) . . (+2,000) . . N Static elaboration (Created page with "'''Q: What does 'static elaboration' do?''' Static elaboration runs after analysis. It modifies the parsetree. During static elaboration: * Identify top-level modules and tr...")
- 12:41, 31 May 2019 (diff | hist) . . (+76) . . Main Page
- 16:03, 30 May 2019 (diff | hist) . . (+1,297) . . N Modules/design units with " default" suffix in their names (Created page with "'''Q: After static elaboration, there are modules/design units with "_default" suffix in their names. Why? And what are they? ''' Static elaboration process is a multiple-ite...")
- 15:56, 30 May 2019 (diff | hist) . . (+201) . . Main Page
- 17:25, 9 May 2019 (diff | hist) . . (+30) . . What are the data structures in Verific? (current)
- 17:21, 9 May 2019 (diff | hist) . . (-2) . . What are the data structures in Verific?
- 17:20, 9 May 2019 (diff | hist) . . (-5) . . What are the data structures in Verific?
- 17:19, 9 May 2019 (diff | hist) . . (-42) . . What are the data structures in Verific?
- 17:18, 9 May 2019 (diff | hist) . . (-6) . . What are the data structures in Verific?
- 17:18, 9 May 2019 (diff | hist) . . (-3) . . What are the data structures in Verific?
- 17:17, 9 May 2019 (diff | hist) . . (+1) . . What are the data structures in Verific?
- 17:17, 9 May 2019 (diff | hist) . . (+3) . . What are the data structures in Verific?
- 17:16, 9 May 2019 (diff | hist) . . (-9) . . What are the data structures in Verific?
- 17:15, 9 May 2019 (diff | hist) . . (+3) . . What are the data structures in Verific?
- 17:15, 9 May 2019 (diff | hist) . . (+11) . . What are the data structures in Verific?
- 17:14, 9 May 2019 (diff | hist) . . (+82) . . What are the data structures in Verific?
- 17:11, 9 May 2019 (diff | hist) . . (-2) . . What are the data structures in Verific?
- 17:09, 9 May 2019 (diff | hist) . . (0) . . What are the data structures in Verific?
- 17:08, 9 May 2019 (diff | hist) . . (-1) . . What are the data structures in Verific?
- 12:03, 9 April 2019 (diff | hist) . . (+1,414) . . Retrieve package name for user-defined variable types (current)
- 12:02, 9 April 2019 (diff | hist) . . (0) . . Main Page
- 12:01, 9 April 2019 (diff | hist) . . (+7) . . Main Page
- 12:41, 3 April 2019 (diff | hist) . . (+787) . . Access attributes of ports in parsetree
- 12:39, 3 April 2019 (diff | hist) . . (+1,864) . . N Access attributes of ports in parsetree (Created page with " <nowiki> #!/usr/bin/perl use strict ; push(@INC, "../pm") ; require "Verific.pm" ; if (!Verific::veri_file::Read("test.v")) { exit 1 ; } my $mod = Verific::veri_file::Get...")
- 12:38, 3 April 2019 (diff | hist) . . (+102) . . Main Page
- 15:20, 7 March 2019 (diff | hist) . . (+3) . . Main Page
- 15:20, 7 March 2019 (diff | hist) . . (+28) . . Main Page
- 16:56, 4 March 2019 (diff | hist) . . (-2) . . Verific data structures
- 16:55, 4 March 2019 (diff | hist) . . (+49) . . Verific data structures
- 16:48, 4 March 2019 (diff | hist) . . (+2,846) . . N Statically elaborate with different values of parameters (Created page with "C++: <nowiki> #include "VeriCopy.h" // Make class VeriMapForCopy available #include "Map.h" // Make class Map available #include "Message.h" // Make m...")
- 16:46, 4 March 2019 (diff | hist) . . (+135) . . Main Page
- 16:25, 4 March 2019 (diff | hist) . . (+6,710) . . N Traverse instances in parsetree (Created page with "C++: <nowiki> // Verific utilities #include "Array.h" // Make class Array available #include "Set.h" // Make class Set available #include "Message.h"...")
- 16:23, 4 March 2019 (diff | hist) . . (+90) . . Main Page
- 17:17, 1 March 2019 (diff | hist) . . (-1) . . Process -f file and explore the Netlist Database (C++) (current)
- 17:16, 1 March 2019 (diff | hist) . . (+5,263) . . Process -f file and explore the Netlist Database (C++)
- 17:15, 1 March 2019 (diff | hist) . . (+1,579) . . N Process -f file and explore the Netlist Database (C++) (Created page with " <nowiki> #include <iostream> #include <fstream> #include "veri_file.h" #include "VeriModule.h" #include "VeriId.h" #include "VeriScope.h" #include "Set.h" using namespace...")
- 17:14, 1 March 2019 (diff | hist) . . (0) . . Process -f file and explore the Netlist Database (py) (current)
- 17:13, 1 March 2019 (diff | hist) . . (+5) . . Main Page
- 17:13, 1 March 2019 (diff | hist) . . (+4,987) . . N Process -f file and explore the Netlist Database (py) (Created page with " <nowiki> #!/usr/bin/python import sys import re sys.path.append('../../../pythonmain/install') import Verific def Accumulate(netlist,done): if not netlist: retu...")
- 17:12, 1 March 2019 (diff | hist) . . (+4) . . Main Page
- 17:12, 1 March 2019 (diff | hist) . . (+131) . . Main Page
- 17:08, 1 March 2019 (diff | hist) . . (+6,847) . . N Process -f file and explore the Netlist Database (Created page with "C++: <nowiki> #include "Map.h" // Make associated hash table class Map available #include "Array.h" // Make associated hash table class Array available #include...") (current)
- 17:07, 1 March 2019 (diff | hist) . . (+128) . . Main Page
- 17:05, 1 March 2019 (diff | hist) . . (+21) . . Main Page
- 16:19, 1 March 2019 (diff | hist) . . (-142) . . Main Page
- 16:18, 1 March 2019 (diff | hist) . . (+3,375) . . N Create a Netlist Database from scratch (not from RTL elaboration) (Created page with " <nowiki> #!/usr/bin/perl use strict; push (@INC,"../../../extra_tests/pm"); require "Verific.pm"; # The global Libset is already at the top of the netlist database. # No ne...")
- 16:18, 1 March 2019 (diff | hist) . . (+150) . . Main Page
- 16:14, 1 March 2019 (diff | hist) . . (+2,074) . . N Pretty-print a module and the packages imported by the module (Created page with "C++: <nowiki> #include <iostream> #include <fstream> #include "veri_file.h" #include "VeriModule.h" #include "VeriId.h" #include "VeriScope.h" #include "Set.h" using names...")
- 16:12, 1 March 2019 (diff | hist) . . (+147) . . Main Page
- 16:02, 1 March 2019 (diff | hist) . . (+2,173) . . N Retrieve package name for user-defined variable types (Created page with "C++ source: <nowiki> #include <iostream> #include "veri_file.h" #include "VeriModule.h" #include "VeriVisitor.h" #include "VeriExpression.h" #include "VeriId.h" using name...")
- 15:50, 1 March 2019 (diff | hist) . . (+131) . . Main Page
- 14:08, 1 March 2019 (diff | hist) . . (+1,722) . . N Extract clock enable (Created page with "Here is a small example which will extract clock-enables for every DFF in the design. It uses both CheckDriverFrom() (to check if there is any potential clock-enable) as well...") (current)
- 14:04, 1 March 2019 (diff | hist) . . (+70) . . Main Page
- 13:54, 1 March 2019 (diff | hist) . . (+3,299) . . N Write out an encrypted netlist (Created page with " <nowiki> #include <iostream> #include <cstring> #include "veri_file.h" #include "DataBase.h" #include "VeriWrite.h" #include "Strings.h" #include "Message.h" #include "Pro...") (current)
- 13:51, 1 March 2019 (diff | hist) . . (+70) . . Main Page
- 13:46, 1 March 2019 (diff | hist) . . (+21) . . Main Page
- 13:40, 1 March 2019 (diff | hist) . . (+14) . . Prettyprint to a string (current)
- 16:18, 28 February 2019 (diff | hist) . . (+1) . . Prettyprint to a string
- 16:17, 28 February 2019 (diff | hist) . . (+64) . . Prettyprint to a string
- 14:11, 28 February 2019 (diff | hist) . . (-8) . . Prettyprint to a string
- 14:10, 28 February 2019 (diff | hist) . . (+5) . . Main Page
- 14:09, 28 February 2019 (diff | hist) . . (+145) . . Prettyprint to a string
- 14:07, 28 February 2019 (diff | hist) . . (0) . . Prettyprint to a string
- 11:46, 27 February 2019 (diff | hist) . . (+258) . . Tcl library path
- 16:48, 21 February 2019 (diff | hist) . . (+15) . . Main Page
- 16:48, 21 February 2019 (diff | hist) . . (-6) . . What languages can I use with Verific software? (current)
- 15:30, 15 February 2019 (diff | hist) . . (+964) . . N Cross-reference between the original RTL files and the elaborated netlist (Created page with "'''Q: Is there a cross-reference between the original RTL design files and the elaborated netlist? We need this for our application. If any issue found in the elaborated netli...") (current)
- 15:19, 15 February 2019 (diff | hist) . . (+197) . . Main Page
- 11:52, 12 February 2019 (diff | hist) . . (+11) . . Design with System Verilog and Verilog 2001 files (current)
- 11:47, 12 February 2019 (diff | hist) . . (+19) . . m Main Page
- 17:41, 28 December 2018 (diff | hist) . . (+1,087) . . Top level module with interface ports (current)
- 17:27, 28 December 2018 (diff | hist) . . (+1,706) . . N Defined macros become undefined - MFCU vs SFCU (Created page with "'''Q: I have macros defined in a separate input file. Why does Verific analyzer complain about "undefined macros" in SystemVerilog mode but not in Verilog 2K mode?''' SystemV...")
- 17:13, 28 December 2018 (diff | hist) . . (+1) . . Main Page
- 17:12, 28 December 2018 (diff | hist) . . (+157) . . Main Page
- 17:04, 28 December 2018 (diff | hist) . . (+24) . . Main Page
- 16:19, 28 December 2018 (diff | hist) . . (+851) . . N Top level module with interface ports (Created page with "'''Q: How to elaborate top-level module with interface ports.''' When I elaborate a top-level module with interface ports, Verific issues a warning message and stops the elab...")
- 14:07, 28 December 2018 (diff | hist) . . (+120) . . Main Page
- 10:30, 26 November 2018 (diff | hist) . . (-773) . . Talk:Main Page (Blanked the page) (current)
- 12:26, 11 September 2018 (diff | hist) . . (+119) . . Does Verific support XMR?
- 11:58, 31 August 2018 (diff | hist) . . (+54) . . Support IEEE 1735 encryption standard (current)
- 18:03, 30 August 2018 (diff | hist) . . (+678) . . N Support IEEE 1735 encryption standard (Created page with "'''Q:Does Verific provide support for IEEE 1735 encryption standard?''' Verific does not implement the decryption/encryption algorithms. This task is appropriately reserved t...")
- 18:00, 30 August 2018 (diff | hist) . . (+111) . . Main Page
- 17:11, 24 August 2018 (diff | hist) . . (+20) . . How to get type/initial value of parameters
- 17:10, 24 August 2018 (diff | hist) . . (+3) . . How to ignore parameters/generics in elaboration
- 17:10, 24 August 2018 (diff | hist) . . (+11) . . How to create a Netlist database from scratch (not from RTL input) (current)
- 17:09, 24 August 2018 (diff | hist) . . (+20) . . How to ignore parameters/generics in elaboration
- 17:01, 24 August 2018 (diff | hist) . . (+3,381) . . N How to create a Netlist database from scratch (not from RTL input) (Created page with "A Perl example: <nowiki> #!/usr/bin/perl use strict; push (@INC,"../../../extra_tests/pm"); require "Verific.pm"; # The global Libset is already at the top of the netlist...")
- 17:00, 24 August 2018 (diff | hist) . . (+142) . . Main Page
- 16:58, 24 August 2018 (diff | hist) . . (+31) . . Main Page
- 16:39, 24 August 2018 (diff | hist) . . (+299) . . Message handling
- 15:37, 24 August 2018 (diff | hist) . . (+865) . . N How to check for errors in analysis/elaboration (Created page with "'''Q:Verific clears the error count at various steps during analysis/elaboration. Is there a way to tell if these processes have errors?''' Verific follows an "optimistic" ap...")
- 15:29, 24 August 2018 (diff | hist) . . (+141) . . Main Page
- 12:42, 24 August 2018 (diff | hist) . . (+526) . . Constant expression replacement
- 12:31, 24 August 2018 (diff | hist) . . (+1,527) . . N How to ignore parameters/generics in elaboration (Created page with "'''Q:Is there a way to tell the elaborator to ignore certain parameters/generics so that the unit/module is not uniquified?''' Specific parameters/generics of specific module...")
- 12:23, 24 August 2018 (diff | hist) . . (+190) . . Main Page
- 12:14, 3 July 2017 (diff | hist) . . (+631) . . N Release version (Created page with "'''Q: How do I tell the version of a Verific software release? ''' The APIs: Message::ReleaseString() Message::ReleaseDate() respectively return the release string (e.g...")
- 12:05, 3 July 2017 (diff | hist) . . (+82) . . Main Page
- 15:02, 26 June 2017 (diff | hist) . . (+992) . . N Tcl library path (Created page with "'''Q: When trying to build, I get the error message: "/usr/bin/ld: cannot find -ltcl". How do I correct that problem?''' First, verify that you have tcl and tcl dev installed...")
- 14:49, 26 June 2017 (diff | hist) . . (+97) . . Main Page
- 16:36, 14 June 2017 (diff | hist) . . (-15) . . How to get type/initial value of parameters
- 13:35, 14 June 2017 (diff | hist) . . (+19) . . Does Verific support XMR?
- 13:34, 14 June 2017 (diff | hist) . . (+1) . . Does Verific support XMR?
- 10:36, 14 June 2017 (diff | hist) . . (+561) . . N How to get enums from Verilog parsetree (Created page with "'''Q: From the parsetree, how can I get the enums declared in a module?''' You can use the following code snippet: VeriModule *mod = ... ; VeriScope *scope = mod->GetSco...") (current)
- 10:32, 14 June 2017 (diff | hist) . . (+123) . . Main Page
- 16:47, 11 May 2017 (diff | hist) . . (+696) . . N How to identify packages being imported into a module (Created page with "'''Q: How do I identify packages being imported into a module?''' Code example: MapIter mi ; VeriModule *mod ; FOREACH_VERILOG_MODULE(mi, mod) { if (!mod || !mod->...") (current)
- 16:46, 11 May 2017 (diff | hist) . . (0) . . Main Page
- 16:46, 11 May 2017 (diff | hist) . . (+129) . . m Main Page
- 15:22, 6 April 2017 (diff | hist) . . (+385) . . N Instance - Module binding order (Created page with "'''Q: Verilog has many ways to find modules not in the file being directly read: -L, -v, -y, .... There may be more than one module of the same name. What is the order of bind...")
- 15:16, 6 April 2017 (diff | hist) . . (+100) . . Main Page
- 14:42, 6 April 2017 (diff | hist) . . (+741) . . N How to find port dimensions (Created page with "'''Q: How do I get port dimensions?''' A port can have multiple (packed/unpacked) dimensions like "module test (input [1:0][2:3] in1 [4:5][6:7]);". Below is a code excerpt in...") (current)
- 14:39, 6 April 2017 (diff | hist) . . (+75) . . Main Page
- 16:33, 5 April 2017 (diff | hist) . . (+836) . . N How to get library containing nested module (Created page with "'''Q: How do I get the library that contains the module nested inside another module?''' Take the following example: 1 module top (output o, input i1, i2, i3); 2 logic...")
- 16:26, 5 April 2017 (diff | hist) . . (+141) . . Main Page
- 12:55, 5 April 2017 (diff | hist) . . (+3) . . What languages can I use with Verific software?
- 16:45, 22 March 2017 (diff | hist) . . (+1,896) . . N How to get linefile information of macro definitions (Created page with "'''Q: How do I get linefile information of macro definitions?''' Take the following example: 1 `define A 2 `define B 10 3 `define C(a) a 4 `define D(a, b) a + b 5...") (current)
- 16:31, 22 March 2017 (diff | hist) . . (+126) . . m Main Page
- 15:03, 16 March 2017 (diff | hist) . . (-85) . . Does Verific support XMR?
- 13:29, 10 February 2017 (diff | hist) . . (+1) . . How to change name of id in Verilog parsetree
- 13:29, 10 February 2017 (diff | hist) . . (+433) . . N How to change name of id in Verilog parsetree (Created page with "'''Q:How do I change the name of an id (VeriIdDef) in Verilog parsetree?''' Name of identifier can be changed using following steps: 1. Get the scope where identifier is dec...")
- 13:23, 10 February 2017 (diff | hist) . . (+131) . . m Main Page
- 13:20, 8 December 2016 (diff | hist) . . (+145) . . m Original RTL language (current)
- 12:50, 29 November 2016 (diff | hist) . . (+10) . . m What VeriModule* or VhdlPrimaryUnit* the Netlist comes from?
- 12:48, 29 November 2016 (diff | hist) . . (-1) . . m Main Page
- 12:47, 29 November 2016 (diff | hist) . . (+11) . . m Main Page
- 12:44, 29 November 2016 (diff | hist) . . (+9) . . m Design with VHDL-1993 and VHDL-2008 files (current)
- 12:42, 29 November 2016 (diff | hist) . . (+1) . . SystemVerilog "std" package
- 12:42, 29 November 2016 (diff | hist) . . (+6) . . Constant expression replacement
- 12:39, 29 November 2016 (diff | hist) . . (+14) . . Compile-time/run-time flags
- 12:37, 29 November 2016 (diff | hist) . . (+1) . . Design with System Verilog and Verilog 2001 files
- 12:27, 29 November 2016 (diff | hist) . . (+607) . . m Message handling
- 11:53, 29 November 2016 (diff | hist) . . (+135) . . m Remove Verific data structures
- 14:50, 23 November 2016 (diff | hist) . . (-5) . . m Remove Verific data structures
- 16:29, 22 November 2016 (diff | hist) . . (+910) . . m How to get all Verilog files being analyzed
- 15:55, 26 October 2016 (diff | hist) . . (+1,842) . . N How to get type/initial value of parameters (Created page with "'''Q: Why do I get type and initial value of parameters?''' Example Perl code: #!/usr/bin/perl # push(@INC,"../../../perlmain/install"); require "Verific.pm"; #...")
- 15:49, 26 October 2016 (diff | hist) . . (+106) . . Main Page
- 15:43, 26 October 2016 (diff | hist) . . (+90) . . Main Page
- 15:43, 26 October 2016 (diff | hist) . . (+430) . . N Prettyprint to a string (Created page with "'''Q: Why do I prettyprint a Verilog parsetree node to a string?''' Example code: VeriExpression *init_value = param_id -> GetInitialValue(); if (init_value)...")
- 11:49, 22 September 2016 (diff | hist) . . (+413) . . m Does Verific support XMR?
- 16:15, 4 August 2016 (diff | hist) . . (+5) . . m Main Page
- 16:14, 4 August 2016 (diff | hist) . . (+602) . . N Message handling (Created page with "'''Q: How do I upgrade/downgrade messages from Verific?''' For C++, use the following APIs: Message::SetMessageType() - Force a message type by message id Message::Ge...")
- 16:08, 4 August 2016 (diff | hist) . . (+71) . . m Main Page
- 16:33, 1 August 2016 (diff | hist) . . (+1) . . Constant expression replacement
- 16:32, 1 August 2016 (diff | hist) . . (+495) . . N Constant expression replacement (Created page with "'''Q: Does Verific replace constant expressions with their respective values?''' I have in my Verilog code: parameter size = 8; reg [size-1:0] foo; I expect the range...")
- 16:28, 1 August 2016 (diff | hist) . . (+121) . . m Main Page
- 11:43, 28 July 2016 (diff | hist) . . (-12) . . Remove Verific data structures
- 11:42, 28 July 2016 (diff | hist) . . (-32) . . m Remove Verific data structures
- 11:41, 28 July 2016 (diff | hist) . . (+24) . . m Remove Verific data structures
- 16:13, 27 July 2016 (diff | hist) . . (+11) . . m Main Page
- 16:12, 27 July 2016 (diff | hist) . . (+879) . . N SystemVerilog "std" package (Created page with "'''Q: Support for SystemVerilog semaphore/process/mailbox.''' When I analyzed my SystemVerilog file, Verific issued error message: test.sv(4): ERROR: process is not declare...")
- 16:05, 27 July 2016 (diff | hist) . . (+1) . . m Main Page
- 16:04, 27 July 2016 (diff | hist) . . (+97) . . m Main Page
- 16:02, 27 July 2016 (diff | hist) . . (+21) . . m Main Page
- 16:02, 27 July 2016 (diff | hist) . . (0) . . m Main Page
- 16:00, 27 July 2016 (diff | hist) . . (+65) . . m Main Page
- 15:46, 27 July 2016 (diff | hist) . . (-2) . . m Compile-time/run-time flags
- 15:40, 27 July 2016 (diff | hist) . . (+3) . . Compile-time/run-time flags
- 15:39, 27 July 2016 (diff | hist) . . (+790) . . N Compile-time/run-time flags (Created page with "'''Q: Are there options to control Verific software's behavior?''' There are compile-time flags and run-time flags to control Verific software's behavior. The compile-time f...")
- 15:29, 27 July 2016 (diff | hist) . . (+94) . . m Main Page
- 15:34, 26 July 2016 (diff | hist) . . (+1,053) . . N Included files associated with a Verilog source file (Created page with "'''Q: How do I get the list of included files associated with a Verilog source file?''' The main utility you require is: static Map *veri_file::GetIncludedFiles() ; It re...")
- 15:31, 26 July 2016 (diff | hist) . . (+140) . . m Main Page
- 15:01, 26 July 2016 (diff | hist) . . (+617) . . N Remove Verific data structures (Created page with "'''Q: How do I remove all Verific data structures in memory?''' To remove Verilog parsetree: veri_file::ResetParser(); To remove VHDL parsetree: vhdl_file::ResetPa...")
- 14:51, 26 July 2016 (diff | hist) . . (+94) . . m Main Page
- 14:15, 25 July 2016 (diff | hist) . . (+23) . . m How to get all Verilog files being analyzed
- 14:11, 25 July 2016 (diff | hist) . . (+107) . . m How to get all Verilog files being analyzed
- 19:10, 22 July 2016 (diff | hist) . . (+7) . . m Main Page
- 18:36, 22 July 2016 (diff | hist) . . (+10) . . m Main Page
- 18:34, 22 July 2016 (diff | hist) . . (+327) . . N Output file formats (Created page with "'''Q: What language formats does Verific software support as output?''' Verific software can write out: * RTL Verilog/SystemVerilog (from parsetree) * RTL VHDL (from parsetr...") (current)
- 18:30, 22 July 2016 (diff | hist) . . (0) . . m Main Page
- 18:30, 22 July 2016 (diff | hist) . . (-2) . . m Main Page
- 18:29, 22 July 2016 (diff | hist) . . (+64) . . m Main Page
- 17:54, 22 July 2016 (diff | hist) . . (+38) . . m Design with System Verilog and Verilog 2001 files
- 17:12, 22 July 2016 (diff | hist) . . (+17) . . m Does Verific support XMR?
- 17:10, 22 July 2016 (diff | hist) . . (+32) . . m Verific data structures
- 17:03, 22 July 2016 (diff | hist) . . (+24) . . m Does Verific build CDFG?
- 17:02, 22 July 2016 (diff | hist) . . (+275) . . N What languages can I use with Verific software? (Created page with "'''Q: What programming languages can I use with Verific software?''' Verific software is written in C++. But with [http://www.swig.org/ SWIG], all APIs are ported to Tcl, Pe...")
- 16:57, 22 July 2016 (diff | hist) . . (+118) . . m Main Page
- 16:56, 22 July 2016 (diff | hist) . . (-117) . . Main Page (Undo revision 211 by Hoa (talk))
- 16:54, 22 July 2016 (diff | hist) . . (+117) . . m Main Page
- 16:43, 22 July 2016 (diff | hist) . . (+8) . . m Main Page
- 16:43, 22 July 2016 (diff | hist) . . (0) . . m Verific data structures
- 16:03, 22 July 2016 (diff | hist) . . (+847) . . N How to get all Verilog files being analyzed (Created page with "'''Q: I'm using -v, -y, .... After Verific is done with the analysis, how do I get a list of all the files being analyzed?''' Use this code: Array analyzed_files ; // Array...")
- 16:03, 22 July 2016 (diff | hist) . . (+26) . . m Main Page
- 16:01, 22 July 2016 (diff | hist) . . (+672) . . N What VeriModule* or VhdlPrimaryUnit* the Netlist comes from? (Created page with "'''Q: While looking at a Netlist, is there a clean way to look back at what VeriModule* or VhdlPrimaryUnit* this netlist was derived from? ''' For example, a module: mod...")
- 16:01, 22 July 2016 (diff | hist) . . (+34) . . m Main Page
- 15:58, 22 July 2016 (diff | hist) . . (+1,602) . . N Verilog Port Expressions (Created page with "'''Q: Why are the ports in original Verilog file renamed to p1, p2, ....?''' Input file: module foo ( datain[0], datain[0] →same net into multiple port expression: ,...")
- 15:58, 22 July 2016 (diff | hist) . . (+8) . . m Main Page
- 15:57, 22 July 2016 (diff | hist) . . (-1) . . m Design with System Verilog and Verilog 2001 files
- 15:56, 22 July 2016 (diff | hist) . . (+875) . . N Design with System Verilog and Verilog 2001 files (Created page with "'''Q: For a design consisting of a mixture of Verilog 2001 and SystemVerilog input files, should I parse all the files as SystemVerilog?''' The set of SystemVerilog construc...")
- 15:56, 22 July 2016 (diff | hist) . . (+17) . . m Main Page
- 15:51, 22 July 2016 (diff | hist) . . (-84) . . m Design with VHDL-1993 and VHDL-2008 files
- 15:51, 22 July 2016 (diff | hist) . . (+739) . . N Design with VHDL-1993 and VHDL-2008 files (Created page with "'''Q: A customer wants to analyze/elaborate different VHDL flavors (1993 and 2008). They want to process the 93 files first and then the 08. As each flavor has its own IEEE li...")
- 15:50, 22 July 2016 (diff | hist) . . (-80) . . m Main Page
- 15:46, 22 July 2016 (diff | hist) . . (+9) . . m How to get module ports from Verilog parsetree (current)
- 15:45, 22 July 2016 (diff | hist) . . (+240) . . N Original RTL language (Created page with "'''Q: How do I know what language a Netlist in the netlist database comes from?''' Use attribute " language" (note the leading space): Netlist *nl; nl->GetAttValue("...")
- 15:44, 22 July 2016 (diff | hist) . . (+8) . . m Main Page
- 15:42, 22 July 2016 (diff | hist) . . (0) . . m Does Verific build CDFG?
- 15:41, 22 July 2016 (diff | hist) . . (+6) . . Does Verific build CDFG?
- 15:41, 22 July 2016 (diff | hist) . . (+65) . . m Does Verific build CDFG?
- 15:39, 22 July 2016 (diff | hist) . . (+852) . . N Does Verific support XMR? (Created page with "'''Q: Does Verific support cross module references (XMR)?''' Verific fully supports XMR with "hierarchy tree" feature. Please refer to http://www.verific.com/docs/index.php?t...")
- 15:39, 22 July 2016 (diff | hist) . . (-1) . . Main Page
- 15:37, 22 July 2016 (diff | hist) . . (+1,891) . . N Verific data structures (Created page with "'''Q: What are the data structures in Verific?''' There are 2 data structures in Verific: parsetree and netlist database. 1. The parsetree is just another representation of...")
- 15:36, 22 July 2016 (diff | hist) . . (+6) . . m Main Page
- 15:35, 22 July 2016 (diff | hist) . . (+1,891) . . N Verific data structure (Created page with "'''Q: What are the data structures in Verific?''' There are 2 data structures in Verific: parsetree and netlist database. 1. The parsetree is just another representation of...") (current)
- 14:29, 22 July 2016 (diff | hist) . . (-6) . . Main Page (Undo revision 184 by Hoa (talk))
- 14:27, 22 July 2016 (diff | hist) . . (+6) . . Main Page
- 14:26, 22 July 2016 (diff | hist) . . (+166) . . m How to get module ports from Verilog parsetree
- 14:21, 22 July 2016 (diff | hist) . . (+8) . . m How to get module ports from Verilog parsetree
- 13:07, 22 July 2016 (diff | hist) . . (+380) . . N How to get module ports from Verilog parsetree (Created page with "From the Verilog parsetree, how can I get the ports of a module? You can use the following APIs: VeriModule::GetPorts() to get the ports (Array of VeriIdDef *) from a module...")
- 13:04, 22 July 2016 (diff | hist) . . (+119) . . Main Page
- 13:01, 22 July 2016 (diff | hist) . . (+1) . . m Main Page (Undo revision 178 by Hoa (talk))
- 13:00, 22 July 2016 (diff | hist) . . (-1) . . m Main Page
- 12:58, 22 July 2016 (diff | hist) . . (+18) . . m Does Verific build CDFG?
- 12:58, 22 July 2016 (diff | hist) . . (+85) . . N Does Verific build CDFG? (Created page with "No, it does not. See [http://www.verific.com/faq/index.php?title=What_are_the_data].")
- 12:57, 22 July 2016 (diff | hist) . . (+88) . . m Main Page
- 12:55, 22 July 2016 (diff | hist) . . (+298) . . m What are the data (current)
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