User contributions
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- 11:35, 23 April 2024 (diff | hist) . . (+3,785) . . N Using TypeRange table to retrieve the originating type-range for an id (Created page with "C++: <nowiki> #include "veri_file.h" #include "DataBase.h" #include "Map.h" #include "Set.h" #ifdef VERIFIC_NAMESPACE using namespace Verific ; #endif int main() { Runt...") (current)
- 11:30, 23 April 2024 (diff | hist) . . (+190) . . Main Page (current)
- 19:52, 3 April 2024 (diff | hist) . . (+52) . . In Verilog parsetree adding names to unnamed instances (current)
- 17:05, 28 February 2024 (diff | hist) . . (+114) . . SystemVerilog "std" package (current)
- 17:41, 25 January 2024 (diff | hist) . . (-6) . . Instance - Module binding order (current)
- 09:51, 17 November 2023 (diff | hist) . . (-1) . . Constant expression replacement (current)
- 21:53, 31 October 2023 (diff | hist) . . (-5) . . Notes on analysis (current)
- 21:52, 31 October 2023 (diff | hist) . . (+136) . . Notes on analysis
- 12:13, 20 October 2023 (diff | hist) . . (0) . . Notes on analysis
- 09:32, 20 October 2023 (diff | hist) . . (+126) . . Notes on analysis
- 17:25, 11 October 2023 (diff | hist) . . (+268) . . How to get best support from Verific (current)
- 14:15, 10 October 2023 (diff | hist) . . (-8) . . How to change name of id in Verilog parsetree (current)
- 10:59, 29 September 2023 (diff | hist) . . (-86) . . Traverse instances in parsetree (current)
- 10:57, 29 September 2023 (diff | hist) . . (+367) . . Traverse instances in parsetree
- 13:19, 22 August 2023 (diff | hist) . . (+3,244) . . N Finding hierarchical paths of a Netlist (Created page with "This application displays all hierarchical paths of Netlist of Cell 'bot1' in the Netlist Database. <nowiki> #include "veri_file.h" #include "DataBase.h" #include "Strings.h...") (current)
- 13:12, 22 August 2023 (diff | hist) . . (+102) . . Main Page
- 14:49, 8 August 2023 (diff | hist) . . (-2) . . Static elaboration
- 14:49, 8 August 2023 (diff | hist) . . (+43) . . Static elaboration
- 14:48, 8 August 2023 (diff | hist) . . (+31) . . Static elaboration
- 12:34, 2 August 2023 (diff | hist) . . (+1,679) . . N How to use RegisterPragmaRefCallBack() (Created page with "Here is a small example showing how to use RegisterPragmaRefCallBack(): <nowiki> #include <iostream> #include "veri_file.h" #include "vhdl_file.h" #include "Message.h" usin...") (current)
- 12:25, 2 August 2023 (diff | hist) . . (+96) . . Main Page
- 08:40, 26 July 2023 (diff | hist) . . (+57) . . How to get linefile data of macros - Macro callback function
- 08:51, 16 June 2023 (diff | hist) . . (+90) . . Escaped identifiers in RTL files and in Verific data structures (current)
- 17:23, 5 June 2023 (diff | hist) . . (+1,333) . . Parse select modules only and ignore the rest (current)
- 13:58, 24 April 2023 (diff | hist) . . (+3,728) . . N In Verilog parsetree adding names to unnamed instances (Created page with "In Verilog, each module instantiation should have a name. But name is optional for UDP instantiation and Verilog primitive instantiation. Verific issues a warning for unnamed...")
- 13:50, 24 April 2023 (diff | hist) . . (+1) . . Main Page
- 13:50, 24 April 2023 (diff | hist) . . (+130) . . Main Page
- 15:02, 14 March 2023 (diff | hist) . . (-2) . . Difference between RTL and gate-level simulations - Flipflop with async set and async reset (current)
- 14:59, 14 March 2023 (diff | hist) . . (0) . . Difference between RTL and gate-level simulations - Flipflop with async set and async reset
- 11:23, 24 February 2023 (diff | hist) . . (-34) . . Notes on analysis
- 11:26, 21 February 2023 (diff | hist) . . (+26) . . Instance - Module binding order
- 14:40, 13 February 2023 (diff | hist) . . (+3,195) . . Verilog Port Expressions (current)
- 10:59, 10 February 2023 (diff | hist) . . (+1,742) . . Verilog Port Expressions
- 10:30, 10 February 2023 (diff | hist) . . (-51) . . Main Page
- 10:27, 10 February 2023 (diff | hist) . . (0) . . m Verilog Port Expressions (Hoa moved page Verilog ports being renamed to Verilog Port Expressions)
- 10:27, 10 February 2023 (diff | hist) . . (+38) . . N Verilog ports being renamed (Hoa moved page Verilog ports being renamed to Verilog Port Expressions) (current)
- 15:59, 25 January 2023 (diff | hist) . . (+296) . . How to get best support from Verific
- 10:35, 15 December 2022 (diff | hist) . . (+116) . . Static elaboration
- 15:32, 17 November 2022 (diff | hist) . . (+6,695) . . N Evaluate 'for-generate' loop (Created page with "C++ application: <nowiki> #include "veri_file.h" #include "VeriModule.h" #include "VeriBaseValue_Stat.h" #include "VeriVisitor.h" #include "VeriExpression.h" #include "VeriC...") (current)
- 15:28, 17 November 2022 (diff | hist) . . (+79) . . Main Page
- 15:12, 28 October 2022 (diff | hist) . . (+279) . . How to save computer resources (current)
- 17:49, 24 October 2022 (diff | hist) . . (-1) . . Replacing Verific built-in primitives/operators with user implementations (current)
- 16:27, 7 October 2022 (diff | hist) . . (0) . . Instance - Module binding order
- 17:57, 27 September 2022 (diff | hist) . . (+8) . . Modules with ' 1' ' 2' suffix in their names (current)
- 15:12, 27 September 2022 (diff | hist) . . (+2,091) . . N Modules with ' 1' ' 2' suffix in their names (Created page with "Static elaboration process adds the suffix "_<number>" to the module name when: #Module contains hierarchical identifier(s), and #Hierarchical identifier(s) in that module poi...")
- 15:11, 27 September 2022 (diff | hist) . . (-7) . . Main Page
- 14:46, 27 September 2022 (diff | hist) . . (+7) . . Modules with " 1", " 2", ..., suffix in their names (current)
- 14:45, 27 September 2022 (diff | hist) . . (+22) . . Modules with " 1", " 2", ..., suffix in their names
- 14:44, 27 September 2022 (diff | hist) . . (-34) . . Modules with " 1", " 2", ..., suffix in their names
- 14:42, 27 September 2022 (diff | hist) . . (+676) . . Modules with " 1", " 2", ..., suffix in their names
- 13:54, 27 September 2022 (diff | hist) . . (-3) . . Modules with " 1", " 2", ..., suffix in their names
- 13:53, 27 September 2022 (diff | hist) . . (+44) . . Modules with " 1", " 2", ..., suffix in their names
- 13:52, 27 September 2022 (diff | hist) . . (+1,379) . . N Modules with " 1", " 2", ..., suffix in their names (Created page with "**** Under construction **** Static elaboration process adds the "_<number>" to the module name when: 1) Module contains hierarchical identifier(s), and 2) Hierarchical ident...")
- 13:48, 27 September 2022 (diff | hist) . . (-1) . . Main Page
- 13:47, 27 September 2022 (diff | hist) . . (+163) . . Main Page
- 00:12, 11 September 2022 (diff | hist) . . (0) . . System attributes (current)
- 00:08, 11 September 2022 (diff | hist) . . (+192) . . System attributes
- 16:45, 9 September 2022 (diff | hist) . . (+130) . . How to save computer resources
- 16:43, 9 September 2022 (diff | hist) . . (+1,133) . . How to save computer resources
- 11:08, 26 August 2022 (diff | hist) . . (+17) . . Simple example of visitor pattern (current)
- 19:42, 24 August 2022 (diff | hist) . . (-9) . . How to tell if a module has encrypted contents (current)
- 22:59, 1 August 2022 (diff | hist) . . (0) . . Compile-time/run-time flags
- 22:52, 1 August 2022 (diff | hist) . . (+52) . . Compile-time/run-time flags
- 12:12, 19 July 2022 (diff | hist) . . (+35) . . Prettyprint all modules in the design hierarchy (current)
- 11:46, 19 July 2022 (diff | hist) . . (-8) . . Main Page
- 17:21, 12 May 2022 (diff | hist) . . (-119) . . Simple examples of VHDL visitor pattern (current)
- 17:16, 12 May 2022 (diff | hist) . . (-77) . . Simple examples of VHDL visitor pattern
- 17:16, 12 May 2022 (diff | hist) . . (+2,489) . . N Simple examples of VHDL visitor pattern (Created page with " <nowiki> [hoa@awing0 220512b]$ cat test.cpp #include "vhdl_file.h" #include "VhdlUnits.h" #include "VhdlIdDef.h" #include "VhdlValue_Elab.h" #include "Strings.h" #ifdef VERI...")
- 17:14, 12 May 2022 (diff | hist) . . (+11) . . Main Page
- 17:13, 12 May 2022 (diff | hist) . . (+87) . . Main Page
- 14:22, 3 May 2022 (diff | hist) . . (+30) . . Access attributes in parsetree (current)
- 09:26, 14 April 2022 (diff | hist) . . (+3,558) . . N How to ignore certain modules while analyzing input RTL files (Created page with "The code example below shows how to ignore certain modules in the input RTL files. The ignored modules will not be present in the parsetree. C++ code: <nowiki> #include "Arr...") (current)
- 08:49, 14 April 2022 (diff | hist) . . (+145) . . Main Page
- 15:45, 4 March 2022 (diff | hist) . . (0) . . Black box, empty box, and unknown box (current)
- 15:44, 4 March 2022 (diff | hist) . . (+75) . . Black box, empty box, and unknown box
- 20:05, 10 February 2022 (diff | hist) . . (-66) . . How to save computer resources
- 21:09, 26 January 2022 (diff | hist) . . (-1) . . How to parse a string (current)
- 21:08, 26 January 2022 (diff | hist) . . (-15) . . How to parse a string
- 11:38, 26 January 2022 (diff | hist) . . (+31) . . Notes on analysis
- 12:56, 29 December 2021 (diff | hist) . . (+383) . . Static elaboration
- 21:30, 3 December 2021 (diff | hist) . . (+150) . . System attributes
- 21:26, 3 December 2021 (diff | hist) . . (+135) . . System attributes
- 18:57, 1 December 2021 (diff | hist) . . (+90) . . Black box, empty box, and unknown box
- 17:52, 3 November 2021 (diff | hist) . . (+8) . . Black box, empty box, and unknown box
- 12:38, 27 October 2021 (diff | hist) . . (-21) . . Statically elaborate with different values of parameters (current)
- 12:38, 27 October 2021 (diff | hist) . . (-21) . . Simple example of visitor pattern
- 14:45, 26 October 2021 (diff | hist) . . (+133) . . How to traverse scope hierarchy (current)
- 16:12, 20 October 2021 (diff | hist) . . (-1) . . How to parse a string
- 10:34, 15 October 2021 (diff | hist) . . (-10) . . Main Page
- 10:32, 15 October 2021 (diff | hist) . . (-54) . . How to get best support from Verific
- 09:21, 15 October 2021 (diff | hist) . . (-1) . . Notes on analysis
- 08:52, 15 October 2021 (diff | hist) . . (-1) . . Notes on analysis
- 08:52, 15 October 2021 (diff | hist) . . (+2) . . Notes on analysis
- 08:51, 15 October 2021 (diff | hist) . . (+152) . . Notes on analysis
- 17:49, 14 October 2021 (diff | hist) . . (+1) . . Notes on analysis
- 15:55, 12 October 2021 (diff | hist) . . (+66) . . How to save computer resources
- 11:32, 8 October 2021 (diff | hist) . . (-28) . . Main Page
- 11:31, 8 October 2021 (diff | hist) . . (+108) . . Escaped identifiers in RTL files and in Verific data structures
- 11:13, 8 October 2021 (diff | hist) . . (-33) . . System attributes
- 11:12, 8 October 2021 (diff | hist) . . (+315) . . System attributes
- 20:08, 4 October 2021 (diff | hist) . . (-174) . . Source code customization & Stable release services
- 20:07, 4 October 2021 (diff | hist) . . (+28) . . Source code customization & Stable release services
- 20:06, 4 October 2021 (diff | hist) . . (+3) . . Source code customization & Stable release services
- 19:53, 4 October 2021 (diff | hist) . . (+1) . . Source code customization & Stable release services
- 19:53, 4 October 2021 (diff | hist) . . (+3) . . Source code customization & Stable release services
- 10:07, 30 September 2021 (diff | hist) . . (+3) . . m Source code customization & Stable release services
- 10:00, 30 September 2021 (diff | hist) . . (+206) . . Source code customization & Stable release services
- 09:57, 30 September 2021 (diff | hist) . . (-15) . . Source code customization & Stable release services
- 09:56, 30 September 2021 (diff | hist) . . (+1,763) . . Source code customization & Stable release services
- 09:49, 30 September 2021 (diff | hist) . . (+314) . . N Source code customization & Stable release services (Created page with ">>> Under construction <<< Verific offers two services to licensees: Source Code Customization and Stable Release. On Verific's file system, each of the licensees has a sepa...")
- 09:46, 30 September 2021 (diff | hist) . . (+122) . . Main Page
- 13:59, 28 September 2021 (diff | hist) . . (+3) . . Black box, empty box, and unknown box
- 17:23, 31 August 2021 (diff | hist) . . (+583) . . LineFile data from input files (current)
- 11:39, 9 August 2021 (diff | hist) . . (-1) . . How to get packed dimensions of enum
- 11:39, 9 August 2021 (diff | hist) . . (+714) . . How to get packed dimensions of enum
- 10:24, 6 August 2021 (diff | hist) . . (-265) . . LineFile data from input files
- 09:18, 6 August 2021 (diff | hist) . . (+265) . . LineFile data from input files
- 13:14, 27 July 2021 (diff | hist) . . (+41) . . Accessing and evaluating module's parameters (current)
- 12:44, 27 July 2021 (diff | hist) . . (-4) . . Accessing and evaluating module's parameters
- 12:43, 27 July 2021 (diff | hist) . . (+11) . . Accessing and evaluating module's parameters
- 12:40, 27 July 2021 (diff | hist) . . (+4,589) . . N Accessing and evaluating module's parameters (Created page with " <nowiki> #include "Map.h" #include "Array.h" #include "Strings.h" #include "veri_file.h" #include "VeriBaseValue_Stat.h" #include "VeriModule.h" #include "VeriExpression.h" #...")
- 12:36, 27 July 2021 (diff | hist) . . (+111) . . Main Page
- 12:03, 9 July 2021 (diff | hist) . . (+13) . . Notes on analysis
- 12:03, 9 July 2021 (diff | hist) . . (-3) . . Notes on analysis
- 11:58, 9 July 2021 (diff | hist) . . (-1) . . Notes on analysis
- 10:36, 9 July 2021 (diff | hist) . . (+36) . . Notes on analysis
- 10:31, 9 July 2021 (diff | hist) . . (+39) . . Notes on analysis
- 09:59, 9 July 2021 (diff | hist) . . (+791) . . N Notes on analysis (Created page with "This is a place holder for notes regarding analysis of System Verilog designs. Can I use veri_file::Analyze to read SV input files one by one? Yes. But if you have multiple...")
- 09:52, 9 July 2021 (diff | hist) . . (+59) . . Main Page
- 11:18, 25 June 2021 (diff | hist) . . (+4) . . How to get best support from Verific
- 11:10, 25 June 2021 (diff | hist) . . (+103) . . How to get best support from Verific
- 15:07, 23 June 2021 (diff | hist) . . (+63) . . Remove Verific data structures (current)
- 13:02, 17 June 2021 (diff | hist) . . (+8) . . How to parse a string
- 12:46, 17 June 2021 (diff | hist) . . (+46) . . Main Page
- 12:45, 17 June 2021 (diff | hist) . . (+3) . . How to parse a string
- 12:44, 17 June 2021 (diff | hist) . . (+1,910) . . How to parse a string
- 10:33, 11 June 2021 (diff | hist) . . (-18) . . Defined macros become undefined - MFCU vs SFCU (current)
- 10:33, 11 June 2021 (diff | hist) . . (-51) . . Defined macros become undefined - MFCU vs SFCU
- 10:27, 11 June 2021 (diff | hist) . . (-20) . . How to detect multiple-clock-edge condition in Verilog parsetree (current)
- 10:26, 11 June 2021 (diff | hist) . . (+448) . . How to detect multiple-clock-edge condition in Verilog parsetree
- 10:56, 9 June 2021 (diff | hist) . . (+4,535) . . N How to detect multiple-clock-edge condition in Verilog parsetree (Created page with "Multiple-clock-edge condition is not support for synthesis. For example: always @(posedge clk or negedge clk) out <= in; or in SystemVerilog dialect: always @(ed...")
- 10:43, 9 June 2021 (diff | hist) . . (0) . . Main Page
- 10:41, 9 June 2021 (diff | hist) . . (+151) . . Main Page
- 13:06, 5 May 2021 (diff | hist) . . (+74) . . How to get best support from Verific
- 10:35, 3 May 2021 (diff | hist) . . (-1) . . Remove Verific data structures
- 10:33, 3 May 2021 (diff | hist) . . (-27) . . Remove Verific data structures
- 16:00, 21 April 2021 (diff | hist) . . (+1) . . How Verific elaborator handles blackboxes/unknown boxes (current)
- 11:01, 21 April 2021 (diff | hist) . . (+2,496) . . Simple example of visitor pattern
- 10:58, 21 April 2021 (diff | hist) . . (+1) . . Main Page
- 22:46, 20 April 2021 (diff | hist) . . (0) . . Does Verific support XMR? (current)
- 15:26, 20 April 2021 (diff | hist) . . (+412) . . Pretty-print a module and the packages imported by the module
- 10:08, 20 April 2021 (diff | hist) . . (+128) . . How to get best support from Verific
- 16:11, 19 April 2021 (diff | hist) . . (+1,380) . . Buffering signals and ungrouping (current)
- 16:07, 19 April 2021 (diff | hist) . . (+7,446) . . N Buffering signals and ungrouping (Created page with "During ungrouping (flattening) a hierarchical design, there are nets that need to be merged. The name of the resulting net from the merge will be the name in the highest level...")
- 16:00, 19 April 2021 (diff | hist) . . (+129) . . Main Page
- 11:52, 19 April 2021 (diff | hist) . . (0) . . How to get library containing nested module (current)
- 11:10, 19 April 2021 (diff | hist) . . (+1) . . Main Page
- 11:08, 19 April 2021 (diff | hist) . . (+1,032) . . How to get library containing nested module
- 13:17, 12 April 2021 (diff | hist) . . (+173) . . System attributes
- 13:01, 12 April 2021 (diff | hist) . . (+112) . . System attributes
- 14:17, 8 April 2021 (diff | hist) . . (+5,308) . . N Comment out a line using text based design modification and parsetree modification (Created page with "C++: <nowiki> #include <iostream> #include "veri_file.h" #include "VeriModule.h" #include "VeriStatement.h" #include "Array.h" #include "Strings.h" #include "TextBasedDes...") (current)
- 14:16, 8 April 2021 (diff | hist) . . (0) . . Main Page
- 22:43, 30 March 2021 (diff | hist) . . (+12) . . Main Page
- 22:42, 30 March 2021 (diff | hist) . . (+9,705) . . Where in RTL does it get assigned? (current)
- 14:06, 23 March 2021 (diff | hist) . . (+6,453) . . N Where in RTL does it get assigned? (Created page with "This example illustrates how to find where a signal gets assigned in the RTL code. C++: <nowiki> #include <iostream> #include "veri_file.h" #include "VeriModule.h" #include...")
- 14:06, 23 March 2021 (diff | hist) . . (+2) . . Main Page
- 13:22, 23 March 2021 (diff | hist) . . (+6,453) . . N Where in RTL is it get assigned? (Created page with "This example illustrates how to find where a signal gets assigned in the RTL code. C++: <nowiki> #include <iostream> #include "veri_file.h" #include "VeriModule.h" #include...") (current)
- 13:18, 23 March 2021 (diff | hist) . . (+87) . . Main Page
- 17:05, 18 March 2021 (diff | hist) . . (+5) . . How to save computer resources
- 17:05, 18 March 2021 (diff | hist) . . (-1) . . How to save computer resources
- 17:04, 18 March 2021 (diff | hist) . . (+123) . . How to save computer resources
- 17:02, 18 March 2021 (diff | hist) . . (0) . . How to save computer resources
- 16:30, 18 March 2021 (diff | hist) . . (+293) . . How to save computer resources
- 18:35, 16 March 2021 (diff | hist) . . (+31) . . How to get best support from Verific
- 18:23, 16 March 2021 (diff | hist) . . (0) . . How to get best support from Verific
- 18:11, 16 March 2021 (diff | hist) . . (+127) . . How to get best support from Verific
- 18:02, 16 March 2021 (diff | hist) . . (+190) . . Escaped identifiers in RTL files and in Verific data structures
- 17:57, 16 March 2021 (diff | hist) . . (+73) . . Escaped identifiers in RTL files and in Verific data structures
- 15:15, 16 March 2021 (diff | hist) . . (+13) . . Escaped identifiers in RTL files and in Verific data structures
- 14:57, 16 March 2021 (diff | hist) . . (-4) . . Escaped identifiers in RTL files and in Verific data structures
- 14:57, 16 March 2021 (diff | hist) . . (+38) . . Escaped identifiers in RTL files and in Verific data structures
- 10:29, 16 March 2021 (diff | hist) . . (+27) . . Main Page
- 10:19, 16 March 2021 (diff | hist) . . (+201) . . Escaped identifiers in RTL files and in Verific data structures
- 10:17, 16 March 2021 (diff | hist) . . (+423) . . N Escaped identifiers in RTL files and in Verific data structures (Created page with "'''>>> This page is under construction <<<''' '''Verific data structures: ''' No escaped identifier In netlist outputs and in pretty-print outputs, identifiers are escaped b...")
- 10:11, 16 March 2021 (diff | hist) . . (+151) . . Main Page
- 10:08, 16 March 2021 (diff | hist) . . (+31) . . Main Page
- 10:07, 16 March 2021 (diff | hist) . . (+122) . . How to save computer resources
- 19:36, 15 March 2021 (diff | hist) . . (+234) . . How to save computer resources
- 15:47, 15 March 2021 (diff | hist) . . (+1,615) . . How to get linefile data of macros - Macro callback function
- 15:03, 15 March 2021 (diff | hist) . . (+7) . . Main Page
- 10:04, 15 March 2021 (diff | hist) . . (-67) . . Main Page
- 16:54, 10 March 2021 (diff | hist) . . (+8) . . How to save computer resources
- 16:51, 10 March 2021 (diff | hist) . . (+1,494) . . How to save computer resources
- 15:49, 10 March 2021 (diff | hist) . . (-10) . . Main Page
- 15:48, 10 March 2021 (diff | hist) . . (+252) . . N How to save computer resources (Created page with "'''This page is under construction. ''' - Compile flag VERIFIC_MEMORY_MANAGER - Compile flag DB_USE_PORT_ORDERED_PORTREF - Compile flag VERILOG_QUICK_PARSE_V_FILES - Run...")
- 15:40, 10 March 2021 (diff | hist) . . (+80) . . Main Page
- 17:06, 4 March 2021 (diff | hist) . . (-54) . . Message handling
- 18:12, 25 February 2021 (diff | hist) . . (+14) . . Release version (current)
- 18:11, 25 February 2021 (diff | hist) . . (-2) . . Message handling
- 18:11, 25 February 2021 (diff | hist) . . (-1) . . Message handling
- 18:10, 25 February 2021 (diff | hist) . . (+29) . . Does Verific build CDFG? (current)
- 18:09, 25 February 2021 (diff | hist) . . (+11) . . Does Verific support XMR?
- 15:14, 25 February 2021 (diff | hist) . . (+123) . . Does Verific support XMR?
- 15:11, 25 February 2021 (diff | hist) . . (+4,339) . . N Hierarchy tree RTL elaboration (Created page with "Reference: [https://www.verific.com/faq/index.php?title=Does_Verific_support_XMR%3F Does Verific support XMR?] Synthesizing designs with cross-module referencing needs Hierar...") (current)
- 15:06, 25 February 2021 (diff | hist) . . (+99) . . Main Page
- 21:37, 24 February 2021 (diff | hist) . . (+6) . . How to get best support from Verific
- 18:33, 23 February 2021 (diff | hist) . . (+113) . . Compile-time/run-time flags
- 21:11, 22 February 2021 (diff | hist) . . (+336) . . Replacing Verific built-in primitives/operators with user implementations
- 17:43, 22 February 2021 (diff | hist) . . (-51) . . Replacing Verific built-in primitives/operators with user implementations
- 16:54, 22 February 2021 (diff | hist) . . (+3,480) . . N Replacing Verific built-in primitives/operators with user implementations (Created page with "Below is a C++ application illustrating how to replace Verific's built-in primitives/operators with user implementations. <nowiki> #include <iostream> #include "veri_file.h...")
- 16:39, 22 February 2021 (diff | hist) . . (+170) . . Main Page
- 11:01, 19 February 2021 (diff | hist) . . (+190) . . How to get best support from Verific
- 10:34, 18 February 2021 (diff | hist) . . (+4) . . How to get best support from Verific
- 10:34, 18 February 2021 (diff | hist) . . (+4) . . How to get best support from Verific
- 10:33, 18 February 2021 (diff | hist) . . (+9) . . How to get best support from Verific
- 14:42, 8 February 2021 (diff | hist) . . (-65) . . Release version
- 14:02, 1 February 2021 (diff | hist) . . (+3,820) . . N How to traverse scope hierarchy (Created page with "C++ code: <nowiki> #include <iostream> #include <cstring> // strchr #include "veri_file.h" #include "VeriModule.h" #include "VeriExpression.h" #include "VeriConstVal.h" #inc...")
- 13:54, 1 February 2021 (diff | hist) . . (+85) . . Main Page
- 11:54, 1 February 2021 (diff | hist) . . (+99) . . Tcl library path
- 15:50, 27 January 2021 (diff | hist) . . (+16) . . How to get best support from Verific
- 15:49, 27 January 2021 (diff | hist) . . (-30) . . How to get best support from Verific
- 22:16, 26 January 2021 (diff | hist) . . (+33) . . How to get best support from Verific
- 22:15, 26 January 2021 (diff | hist) . . (+1) . . How to get best support from Verific
- 22:14, 26 January 2021 (diff | hist) . . (+33) . . How to get best support from Verific
- 22:12, 26 January 2021 (diff | hist) . . (0) . . How to get best support from Verific
- 22:11, 26 January 2021 (diff | hist) . . (+39) . . How to get best support from Verific
- 22:10, 26 January 2021 (diff | hist) . . (+227) . . How to get best support from Verific
- 18:59, 26 January 2021 (diff | hist) . . (+138) . . How to get linefile data of macros - Macro callback function
- 18:05, 26 January 2021 (diff | hist) . . (+9,714) . . N How to get linefile data of macros - Macro callback function (Created page with "C++ application: <nowiki> #include <iostream> #include <sstream> #include "veri_file.h" #include "VeriTreeNode.h" #include "Map.h" using namespace std ; #ifdef VERIFIC_N...")
- 18:01, 26 January 2021 (diff | hist) . . (+148) . . Main Page
- 20:20, 7 January 2021 (diff | hist) . . (+10) . . Difference between RTL and gate-level simulations - Flipflop with async set and async reset
- 20:18, 7 January 2021 (diff | hist) . . (-2) . . Difference between RTL and gate-level simulations - Flipflop with async set and async reset
- 15:38, 7 January 2021 (diff | hist) . . (-1) . . Difference between RTL and gate-level simulations - Flipflop with async set and async reset
- 15:36, 7 January 2021 (diff | hist) . . (-3) . . Difference between RTL and gate-level simulations - Flipflop with async set and async reset
- 15:21, 7 January 2021 (diff | hist) . . (+6) . . Difference between RTL and gate-level simulations - Flipflop with async set and async reset
- 15:19, 7 January 2021 (diff | hist) . . (-2) . . Difference between RTL and gate-level simulations - Flipflop with async set and async reset
- 15:15, 7 January 2021 (diff | hist) . . (-98) . . Difference between RTL and gate-level simulations - Flipflop with async set and async reset
- 15:15, 7 January 2021 (diff | hist) . . (+5,337) . . N Difference between RTL and gate-level simulations - Flipflop with async set and async reset (Created page with "'''Difference between RTL and gate-level simulations - Flipflop with async set and async reset''' ''This article is inspired by an article by Clifford E. Cummings and Don Mil...")
- 15:04, 7 January 2021 (diff | hist) . . (+192) . . Main Page
- 13:34, 23 December 2020 (diff | hist) . . (-10) . . Verilog Port Expressions
- 13:33, 23 December 2020 (diff | hist) . . (+10) . . Verilog Port Expressions
- 11:26, 23 December 2020 (diff | hist) . . (+40) . . How Verific elaborator handles blackboxes/unknown boxes
- 10:45, 23 December 2020 (diff | hist) . . (+10) . . How Verific elaborator handles blackboxes/unknown boxes
- 10:00, 23 December 2020 (diff | hist) . . (+861) . . How Verific elaborator handles blackboxes/unknown boxes
- 23:52, 22 December 2020 (diff | hist) . . (-9) . . Black box, empty box, and unknown box
- 23:51, 22 December 2020 (diff | hist) . . (-14) . . How Verific elaborator handles blackboxes/unknown boxes
- 23:50, 22 December 2020 (diff | hist) . . (+14) . . How Verific elaborator handles blackboxes/unknown boxes
- 23:48, 22 December 2020 (diff | hist) . . (+142) . . Black box, empty box, and unknown box
- 23:46, 22 December 2020 (diff | hist) . . (+63) . . How Verific elaborator handles blackboxes/unknown boxes
- 18:45, 22 December 2020 (diff | hist) . . (+3,431) . . N How Verific elaborator handles blackboxes/unknown boxes (Created page with ">> This page is in progress << '''Q: After RTL elaboration on a Verilog design, I see Netlist with names such as 'NamedPorts' or 'OrderedPorts.' Sometimes in the Verilog netl...")
- 18:22, 22 December 2020 (diff | hist) . . (+129) . . Main Page
- 18:18, 22 December 2020 (diff | hist) . . (+10) . . Black box, empty box, and unknown box
- 17:32, 7 December 2020 (diff | hist) . . (+1,033) . . N Simple example of visitor pattern (Created page with " <nowiki> $ cat test.cpp #include <iostream> #include "veri_file.h" #include "VeriModule.h" #include "VeriVisitor.h" #include "VeriConstVal.h" #include "Strings.h" #ifdef V...")
- 17:29, 7 December 2020 (diff | hist) . . (+89) . . Main Page
- 13:49, 7 December 2020 (diff | hist) . . (+2,605) . . N Access attributes in parsetree (Created page with " <nowiki> #include "veri_file.h" #include "VeriModule.h" #include "VeriExpression.h" #include "VeriMisc.h" #include "VeriId.h" #include "Map.h" #include "Array.h" #include "...")
- 13:45, 7 December 2020 (diff | hist) . . (+90) . . Main Page
- 13:18, 7 December 2020 (diff | hist) . . (+242) . . Message handling
- 23:14, 17 November 2020 (diff | hist) . . (+224) . . How to get best support from Verific
- 16:09, 13 November 2020 (diff | hist) . . (+5) . . Main Page
- 16:07, 13 November 2020 (diff | hist) . . (+5,187) . . Type Range example with multi-dimensional arrays (current)
- 15:45, 7 October 2020 (diff | hist) . . (+22) . . LineFile data from input files
- 15:15, 1 October 2020 (diff | hist) . . (+2,137) . . N LineFile data from input files (Created page with "Verific uses the 'LineFile' manager to preserve line/file origination information from HDL source files. This info is annotated on all objects in parse trees and netlist datab...")
- 15:04, 1 October 2020 (diff | hist) . . (+70) . . Main Page
- 14:20, 15 September 2020 (diff | hist) . . (+8) . . How to get best support from Verific
- 12:05, 4 September 2020 (diff | hist) . . (+5) . . Simulation models for Verific primitives (current)
- 12:04, 4 September 2020 (diff | hist) . . (+98) . . N Simulation models for Verific primitives (Created page with "They are in example_designs/verilog/verificmodels.v and example_designs/verilog/verificsvamodels.v")
- 12:03, 4 September 2020 (diff | hist) . . (+143) . . Main Page
- 15:25, 24 August 2020 (diff | hist) . . (+5,984) . . N Fanout cone and grouping (Created page with "C++ code: <nowiki> →This application example collects instances in the fanout cone of a signal, and groups those instances into a new netlist: #include "Set.h" #include...")
- 15:20, 24 August 2020 (diff | hist) . . (+105) . . Main Page
- 10:39, 6 August 2020 (diff | hist) . . (+1,269) . . How to change name of id in Verilog parsetree
- 17:27, 30 July 2020 (diff | hist) . . (+800) . . Black box, empty box, and unknown box
- 17:06, 22 July 2020 (diff | hist) . . (+1,585) . . Included files associated with a Verilog source file (current)
- 16:44, 22 July 2020 (diff | hist) . . (+6) . . Included files associated with a Verilog source file
- 14:49, 20 July 2020 (diff | hist) . . (+2,448) . . N How to parse a string (Created page with "Let's say you want to add a node to the parsetree. One of the simple ways to do so is to start with a text string; then "parse" that string to get a VHDL or Verilog construct...")
- 14:29, 20 July 2020 (diff | hist) . . (+66) . . Main Page
- 14:10, 9 July 2020 (diff | hist) . . (+793) . . Access attributes of ports in parsetree (current)
- 13:01, 23 June 2020 (diff | hist) . . (+2,705) . . N How to create new module in Verilog parsetree (Created page with "This code sample also shows how to add new parameters and new ports to a module. C++: <nowiki> #include <iostream> #include "veri_file.h" #include "veri_tokens.h" #include...") (current)
- 12:58, 23 June 2020 (diff | hist) . . (+113) . . Main Page
- 12:31, 23 June 2020 (diff | hist) . . (+5,317) . . N How to get full hierarchy ID path (Created page with "Note that this code sample requires "Hierarchy Tree" feature. C++ code: <nowiki> #include "VerificSystem.h" #include "veri_file.h" #include "VeriModuleItem.h" #include "Veri...") (current)
- 12:30, 23 June 2020 (diff | hist) . . (-2) . . Main Page
- 12:24, 23 June 2020 (diff | hist) . . (+5,317) . . N Verilog/C++: How to get full hiererachy ID path : How to get full hiererachy ID path (Created page with "Note that this code sample requires "Hierarchy Tree" feature. C++ code: <nowiki> #include "VerificSystem.h" #include "veri_file.h" #include "VeriModuleItem.h" #include "Veri...") (current)
- 12:20, 23 June 2020 (diff | hist) . . (+91) . . Main Page
- 01:36, 15 June 2020 (diff | hist) . . (-300) . . System attributes
- 18:02, 5 June 2020 (diff | hist) . . (+3,126) . . Create a Netlist Database from scratch (not from RTL elaboration)
- 17:58, 5 June 2020 (diff | hist) . . (+4) . . Main Page
- 14:08, 5 June 2020 (diff | hist) . . (-128) . . Black box, empty box, and unknown box
- 17:44, 4 June 2020 (diff | hist) . . (+32) . . Black box, empty box, and unknown box
- 14:49, 4 June 2020 (diff | hist) . . (+11) . . Black box, empty box, and unknown box
- 14:43, 4 June 2020 (diff | hist) . . (+7,550) . . N Black box, empty box, and unknown box (Created page with "In Verific Netlist Database, a Netlist can be a black box, an empty box, or an unknown box. #An unknown box is a Netlist that is #*from an instantiation of an undefined Veril...")
- 14:07, 4 June 2020 (diff | hist) . . (+98) . . Main Page
- 17:47, 2 June 2020 (diff | hist) . . (+2,399) . . Message handling
- 17:29, 2 June 2020 (diff | hist) . . (+40) . . Main Page
- 14:12, 1 June 2020 (diff | hist) . . (+1,657) . . N Parsing from data in memory (Created page with "It is possible to use "stream input" to parse data in memory. The example below is For Verilog input, but it can be adapted to use for VHLD input as well. If you run this ap...") (current)
- 14:07, 1 June 2020 (diff | hist) . . (+82) . . Main Page
- 14:44, 14 May 2020 (diff | hist) . . (+49) . . How to use RegisterCallBackMsg() (current)
- 13:30, 14 May 2020 (diff | hist) . . (+3,157) . . N How to use RegisterCallBackMsg() (Created page with "Here is a small example showing how to use RegisterCallBackMsg(): <nowiki> #include <stdio.h> #include <stdarg.h> #include "Strings.h" #include "Map.h" // Make assoc...")
- 13:25, 14 May 2020 (diff | hist) . . (+84) . . Main Page
- 15:19, 13 May 2020 (diff | hist) . . (-10) . . Main Page
- 15:18, 13 May 2020 (diff | hist) . . (+10) . . Main Page
- 20:05, 8 May 2020 (diff | hist) . . (+1) . . System attributes
- 20:03, 8 May 2020 (diff | hist) . . (+12) . . System attributes
- 13:40, 6 May 2020 (diff | hist) . . (+2) . . What VeriModule* or VhdlPrimaryUnit* the Netlist comes from? (current)
- 13:40, 6 May 2020 (diff | hist) . . (+19) . . What VeriModule* or VhdlPrimaryUnit* the Netlist comes from?
- 13:03, 6 May 2020 (diff | hist) . . (+1) . . Macro Callback example (current)
- 13:12, 28 April 2020 (diff | hist) . . (-2) . . How to get best support from Verific
- 13:11, 28 April 2020 (diff | hist) . . (+318) . . How to get best support from Verific
- 11:09, 28 April 2020 (diff | hist) . . (-4) . . How to get best support from Verific
- 12:06, 26 March 2020 (diff | hist) . . (+39) . . Does Verific support XMR?
- 19:03, 14 February 2020 (diff | hist) . . (+30) . . System attributes
- 12:36, 14 February 2020 (diff | hist) . . (-4) . . System attributes
- 12:35, 14 February 2020 (diff | hist) . . (+2) . . System attributes
- 12:33, 14 February 2020 (diff | hist) . . (+323) . . System attributes
- 12:08, 14 February 2020 (diff | hist) . . (+4) . . System attributes
- 12:07, 14 February 2020 (diff | hist) . . (+2) . . System attributes
- 15:20, 13 February 2020 (diff | hist) . . (+46) . . System attributes
- 14:42, 13 February 2020 (diff | hist) . . (-1) . . System attributes
- 14:42, 13 February 2020 (diff | hist) . . (-40) . . System attributes
- 14:41, 13 February 2020 (diff | hist) . . (+2,540) . . N System attributes (Created page with "Verific system attributes are attributes added and attached to DesignObjs (Design Objects) during the process of building the Netlist Database. To distinguish with user-decla...")
- 14:27, 13 February 2020 (diff | hist) . . (+62) . . Main Page
- 17:04, 12 February 2020 (diff | hist) . . (+2,764) . . N Using stream input to ignore input file (Created page with "This example shows how to use stream input to ignore input files that meet certain conditions. The example uses only filename as the "ignore" category. But you can have other...") (current)
- 16:59, 12 February 2020 (diff | hist) . . (+101) . . Main Page
- 16:02, 10 February 2020 (diff | hist) . . (+9,156) . . N Bit-blasting a multi-port RAM instance (Created page with "'''Q: What is bit-blasting a multi-port RAM instance''' Verific’s RAM extraction creates a minimal-port, multi-port RAM model in the netlist for every identifier that behav...") (current)
- 15:55, 10 February 2020 (diff | hist) . . (+103) . . Main Page
- 18:30, 3 February 2020 (diff | hist) . . (+8) . . Main Page
- 17:53, 31 January 2020 (diff | hist) . . (+4,658) . . Memory elements of a RamNet (current)
- 14:00, 29 January 2020 (diff | hist) . . (+21) . . How to check for errors in analysis/elaboration (current)
- 13:13, 29 January 2020 (diff | hist) . . (0) . . How to check for errors in analysis/elaboration
- 13:12, 29 January 2020 (diff | hist) . . (+69) . . How to check for errors in analysis/elaboration
- 13:07, 29 January 2020 (diff | hist) . . (+257) . . How to check for errors in analysis/elaboration
- 18:27, 22 January 2020 (diff | hist) . . (+1) . . Main Page
- 18:25, 22 January 2020 (diff | hist) . . (+4,836) . . N Type Range example with multi-dimensional arrays (Created page with "For a design with multidimensional arrays, the application needs to create a data structure for mapping NetBus to TypeRange. C++: <nowiki> #include <iostream> #include "veri...")
- 18:21, 22 January 2020 (diff | hist) . . (+127) . . Main Page
- 18:06, 22 January 2020 (diff | hist) . . (+3,406) . . N Memory elements of a RamNet (Created page with "In Verific Netlist Database, a RamNet is created for every identifier in the parsetree that is inferred as multi-port memory. This example checks what memory elements are con...")
- 18:02, 22 January 2020 (diff | hist) . . (+78) . . Main Page
- 17:04, 22 January 2020 (diff | hist) . . (+17) . . Main Page
- 17:53, 21 January 2020 (diff | hist) . . (+1) . . How to tell if a module has encrypted contents
- 17:53, 21 January 2020 (diff | hist) . . (+6,736) . . N How to tell if a module has encrypted contents (Created page with "C++ <nowiki> #include <cstring> // for memset #include "veri_file.h" // Make verilog reader available #include "VeriModule.h" // Definition of a VeriModule...")
- 17:50, 21 January 2020 (diff | hist) . . (+115) . . Main Page
- 17:30, 21 January 2020 (diff | hist) . . (+6) . . How to get best support from Verific
- 16:02, 21 January 2020 (diff | hist) . . (0) . . Visiting Hierarchical References (VeriSelectedName)
- 16:02, 21 January 2020 (diff | hist) . . (+6) . . Visiting Hierarchical References (VeriSelectedName)
- 15:59, 21 January 2020 (diff | hist) . . (+3,014) . . N Visiting Hierarchical References (VeriSelectedName) (Created page with "In Verilog parsetree, hierarchical references are of type VeriSelectedName. Note that the "_suffix_id" fields are resolved only in statically-elaborated parsetree. In other wo...")
- 15:54, 21 January 2020 (diff | hist) . . (+2) . . Main Page
- 15:52, 21 January 2020 (diff | hist) . . (+124) . . Main Page
- 17:58, 22 October 2019 (diff | hist) . . (0) . . How to get all Verilog files being analyzed
- 14:55, 4 October 2019 (diff | hist) . . (+2,118) . . N How to ignore a (not used) parameter/generic in elaboration. (Created page with "'''Q: How do I specify the elaborator to ignore parameter/generic that is not used?''' In RTL or static elaboration, parameterized instances are uniquified. For example, this...") (current)
- 14:37, 4 October 2019 (diff | hist) . . (+144) . . Main Page
- 14:11, 21 August 2019 (diff | hist) . . (+2,642) . . N Getting instances' parameters (Created page with "C++: <nowiki> #include "Map.h" #include "Array.h" #include "veri_file.h" #include "VeriModule.h" #include "VeriExpression.h" #include "VeriId.h" #include "VeriScope.h" #ifd...") (current)
- 14:07, 21 August 2019 (diff | hist) . . (+81) . . Main Page
- 12:21, 14 August 2019 (diff | hist) . . (-27) . . Comment out a line using test-based design modification and parsetree modification (current)
- 13:02, 30 July 2019 (diff | hist) . . (+629) . . Prettyprint all modules in the design hierarchy
- 17:10, 29 July 2019 (diff | hist) . . (-23) . . Prettyprint all modules in the design hierarchy
- 17:08, 29 July 2019 (diff | hist) . . (-1,484) . . Prettyprint all modules in the design hierarchy
- 23:29, 28 July 2019 (diff | hist) . . (-1) . . Prettyprint all modules in the design hierarchy
- 23:28, 28 July 2019 (diff | hist) . . (0) . . Prettyprint all modules in the design hierarchy
- 23:26, 28 July 2019 (diff | hist) . . (-2) . . Prettyprint all modules in the design hierarchy
- 23:25, 28 July 2019 (diff | hist) . . (-14) . . Prettyprint all modules in the design hierarchy
- 23:24, 28 July 2019 (diff | hist) . . (+12) . . Prettyprint all modules in the design hierarchy
- 23:22, 28 July 2019 (diff | hist) . . (+7,879) . . N Prettyprint all modules in the design hierarchy (Created page with "There is an API to prettyprint a module, and there is an API to prettyprint all modules in a library. But there is no single API to prettyprint all modules in the design hier...")
- 23:16, 28 July 2019 (diff | hist) . . (+117) . . Main Page
- 16:19, 22 July 2019 (diff | hist) . . (+9) . . Logic optimization across hierarchy boundaries (current)
- 16:19, 22 July 2019 (diff | hist) . . (+9) . . Logic optimization across hierarchy boundaries
- 16:17, 22 July 2019 (diff | hist) . . (+1,446) . . N Logic optimization across hierarchy boundaries (Created page with "Does Verific support design optimizations such as constant propagation and dead-code elimination across hierarchies? The optimization done during elaboration flow in Verific...")
- 16:15, 22 July 2019 (diff | hist) . . (+142) . . Main Page
- 15:30, 22 July 2019 (diff | hist) . . (+5,335) . . N Comment out a line using test-based design modification and parsetree modification (Created page with "C++: <nowiki> #include <iostream> #include "veri_file.h" #include "VeriModule.h" #include "VeriStatement.h" #include "Array.h" #include "Strings.h" #include "TextBasedDes...")
- 15:29, 22 July 2019 (diff | hist) . . (+104) . . Main Page
- 15:20, 16 July 2019 (diff | hist) . . (+2,194) . . N How to get best support from Verific (Created page with "We here at Verific strive try to provide you with the best customer service. But we need help from you. Please: * Identify your company and your group/business unit. Many of...")
- 15:16, 16 July 2019 (diff | hist) . . (+24) . . Main Page
- 18:14, 4 July 2019 (diff | hist) . . (-2) . . How to make lives easier (current)
- 18:13, 4 July 2019 (diff | hist) . . (+374) . . How to make lives easier
- 17:57, 4 July 2019 (diff | hist) . . (-14) . . How to make lives easier
- 17:57, 4 July 2019 (diff | hist) . . (+10) . . Main Page
- 17:55, 4 July 2019 (diff | hist) . . (+2,450) . . N How to make lives easier (Created page with "We here at Verific strive try to provide you with the best customer service. But we need help from you. Together, we'll make our lives easier. So we request you: * Identify...")
- 17:45, 4 July 2019 (diff | hist) . . (+58) . . Main Page
- 16:21, 4 July 2019 (diff | hist) . . (-5) . . How to get packed dimensions of enum
- 16:20, 4 July 2019 (diff | hist) . . (+5,511) . . N How to get packed dimensions of enum (Created page with "C++: <nowiki> #include "Map.h" // Make associated hash table class Map available #include "Set.h" // Make associated hash table class Set available #include "...")
- 16:16, 4 July 2019 (diff | hist) . . (+101) . . Main Page
- 21:19, 11 June 2019 (diff | hist) . . (+171) . . How to get all Verilog files being analyzed
- 18:01, 11 June 2019 (diff | hist) . . (-7) . . How to get all Verilog files being analyzed
- 12:53, 31 May 2019 (diff | hist) . . (+2,000) . . N Static elaboration (Created page with "'''Q: What does 'static elaboration' do?''' Static elaboration runs after analysis. It modifies the parsetree. During static elaboration: * Identify top-level modules and tr...")
- 12:41, 31 May 2019 (diff | hist) . . (+76) . . Main Page
- 16:03, 30 May 2019 (diff | hist) . . (+1,297) . . N Modules/design units with " default" suffix in their names (Created page with "'''Q: After static elaboration, there are modules/design units with "_default" suffix in their names. Why? And what are they? ''' Static elaboration process is a multiple-ite...")
- 15:56, 30 May 2019 (diff | hist) . . (+201) . . Main Page
- 17:25, 9 May 2019 (diff | hist) . . (+30) . . What are the data structures in Verific? (current)
- 17:21, 9 May 2019 (diff | hist) . . (-2) . . What are the data structures in Verific?
- 17:20, 9 May 2019 (diff | hist) . . (-5) . . What are the data structures in Verific?
- 17:19, 9 May 2019 (diff | hist) . . (-42) . . What are the data structures in Verific?
- 17:18, 9 May 2019 (diff | hist) . . (-6) . . What are the data structures in Verific?
- 17:18, 9 May 2019 (diff | hist) . . (-3) . . What are the data structures in Verific?
- 17:17, 9 May 2019 (diff | hist) . . (+1) . . What are the data structures in Verific?
- 17:17, 9 May 2019 (diff | hist) . . (+3) . . What are the data structures in Verific?
- 17:16, 9 May 2019 (diff | hist) . . (-9) . . What are the data structures in Verific?
- 17:15, 9 May 2019 (diff | hist) . . (+3) . . What are the data structures in Verific?
- 17:15, 9 May 2019 (diff | hist) . . (+11) . . What are the data structures in Verific?
- 17:14, 9 May 2019 (diff | hist) . . (+82) . . What are the data structures in Verific?
- 17:11, 9 May 2019 (diff | hist) . . (-2) . . What are the data structures in Verific?
- 17:09, 9 May 2019 (diff | hist) . . (0) . . What are the data structures in Verific?
- 17:08, 9 May 2019 (diff | hist) . . (-1) . . What are the data structures in Verific?
- 12:03, 9 April 2019 (diff | hist) . . (+1,414) . . Retrieve package name for user-defined variable types (current)
- 12:02, 9 April 2019 (diff | hist) . . (0) . . Main Page
- 12:01, 9 April 2019 (diff | hist) . . (+7) . . Main Page
- 12:41, 3 April 2019 (diff | hist) . . (+787) . . Access attributes of ports in parsetree
- 12:39, 3 April 2019 (diff | hist) . . (+1,864) . . N Access attributes of ports in parsetree (Created page with " <nowiki> #!/usr/bin/perl use strict ; push(@INC, "../pm") ; require "Verific.pm" ; if (!Verific::veri_file::Read("test.v")) { exit 1 ; } my $mod = Verific::veri_file::Get...")
- 12:38, 3 April 2019 (diff | hist) . . (+102) . . Main Page
- 15:20, 7 March 2019 (diff | hist) . . (+3) . . Main Page
- 15:20, 7 March 2019 (diff | hist) . . (+28) . . Main Page
- 16:56, 4 March 2019 (diff | hist) . . (-2) . . Verific data structures
- 16:55, 4 March 2019 (diff | hist) . . (+49) . . Verific data structures
- 16:48, 4 March 2019 (diff | hist) . . (+2,846) . . N Statically elaborate with different values of parameters (Created page with "C++: <nowiki> #include "VeriCopy.h" // Make class VeriMapForCopy available #include "Map.h" // Make class Map available #include "Message.h" // Make m...")
- 16:46, 4 March 2019 (diff | hist) . . (+135) . . Main Page
- 16:25, 4 March 2019 (diff | hist) . . (+6,710) . . N Traverse instances in parsetree (Created page with "C++: <nowiki> // Verific utilities #include "Array.h" // Make class Array available #include "Set.h" // Make class Set available #include "Message.h"...")
- 16:23, 4 March 2019 (diff | hist) . . (+90) . . Main Page
- 17:17, 1 March 2019 (diff | hist) . . (-1) . . Process -f file and explore the Netlist Database (C++) (current)
- 17:16, 1 March 2019 (diff | hist) . . (+5,263) . . Process -f file and explore the Netlist Database (C++)
- 17:15, 1 March 2019 (diff | hist) . . (+1,579) . . N Process -f file and explore the Netlist Database (C++) (Created page with " <nowiki> #include <iostream> #include <fstream> #include "veri_file.h" #include "VeriModule.h" #include "VeriId.h" #include "VeriScope.h" #include "Set.h" using namespace...")
- 17:14, 1 March 2019 (diff | hist) . . (0) . . Process -f file and explore the Netlist Database (py) (current)
- 17:13, 1 March 2019 (diff | hist) . . (+5) . . Main Page
- 17:13, 1 March 2019 (diff | hist) . . (+4,987) . . N Process -f file and explore the Netlist Database (py) (Created page with " <nowiki> #!/usr/bin/python import sys import re sys.path.append('../../../pythonmain/install') import Verific def Accumulate(netlist,done): if not netlist: retu...")
- 17:12, 1 March 2019 (diff | hist) . . (+4) . . Main Page
- 17:12, 1 March 2019 (diff | hist) . . (+131) . . Main Page
- 17:08, 1 March 2019 (diff | hist) . . (+6,847) . . N Process -f file and explore the Netlist Database (Created page with "C++: <nowiki> #include "Map.h" // Make associated hash table class Map available #include "Array.h" // Make associated hash table class Array available #include...") (current)
- 17:07, 1 March 2019 (diff | hist) . . (+128) . . Main Page
- 17:05, 1 March 2019 (diff | hist) . . (+21) . . Main Page
- 16:19, 1 March 2019 (diff | hist) . . (-142) . . Main Page
- 16:18, 1 March 2019 (diff | hist) . . (+3,375) . . N Create a Netlist Database from scratch (not from RTL elaboration) (Created page with " <nowiki> #!/usr/bin/perl use strict; push (@INC,"../../../extra_tests/pm"); require "Verific.pm"; # The global Libset is already at the top of the netlist database. # No ne...")
- 16:18, 1 March 2019 (diff | hist) . . (+150) . . Main Page
- 16:14, 1 March 2019 (diff | hist) . . (+2,074) . . N Pretty-print a module and the packages imported by the module (Created page with "C++: <nowiki> #include <iostream> #include <fstream> #include "veri_file.h" #include "VeriModule.h" #include "VeriId.h" #include "VeriScope.h" #include "Set.h" using names...")
- 16:12, 1 March 2019 (diff | hist) . . (+147) . . Main Page
- 16:02, 1 March 2019 (diff | hist) . . (+2,173) . . N Retrieve package name for user-defined variable types (Created page with "C++ source: <nowiki> #include <iostream> #include "veri_file.h" #include "VeriModule.h" #include "VeriVisitor.h" #include "VeriExpression.h" #include "VeriId.h" using name...")
- 15:50, 1 March 2019 (diff | hist) . . (+131) . . Main Page
- 14:08, 1 March 2019 (diff | hist) . . (+1,722) . . N Extract clock enable (Created page with "Here is a small example which will extract clock-enables for every DFF in the design. It uses both CheckDriverFrom() (to check if there is any potential clock-enable) as well...") (current)
- 14:04, 1 March 2019 (diff | hist) . . (+70) . . Main Page
- 13:54, 1 March 2019 (diff | hist) . . (+3,299) . . N Write out an encrypted netlist (Created page with " <nowiki> #include <iostream> #include <cstring> #include "veri_file.h" #include "DataBase.h" #include "VeriWrite.h" #include "Strings.h" #include "Message.h" #include "Pro...") (current)
- 13:51, 1 March 2019 (diff | hist) . . (+70) . . Main Page
- 13:46, 1 March 2019 (diff | hist) . . (+21) . . Main Page
- 13:40, 1 March 2019 (diff | hist) . . (+14) . . Prettyprint to a string (current)
- 16:18, 28 February 2019 (diff | hist) . . (+1) . . Prettyprint to a string
- 16:17, 28 February 2019 (diff | hist) . . (+64) . . Prettyprint to a string
- 14:11, 28 February 2019 (diff | hist) . . (-8) . . Prettyprint to a string
- 14:10, 28 February 2019 (diff | hist) . . (+5) . . Main Page
- 14:09, 28 February 2019 (diff | hist) . . (+145) . . Prettyprint to a string
- 14:07, 28 February 2019 (diff | hist) . . (0) . . Prettyprint to a string
- 11:46, 27 February 2019 (diff | hist) . . (+258) . . Tcl library path
- 16:48, 21 February 2019 (diff | hist) . . (+15) . . Main Page
- 16:48, 21 February 2019 (diff | hist) . . (-6) . . What languages can I use with Verific software? (current)
- 15:30, 15 February 2019 (diff | hist) . . (+964) . . N Cross-reference between the original RTL files and the elaborated netlist (Created page with "'''Q: Is there a cross-reference between the original RTL design files and the elaborated netlist? We need this for our application. If any issue found in the elaborated netli...") (current)
- 15:19, 15 February 2019 (diff | hist) . . (+197) . . Main Page
- 11:52, 12 February 2019 (diff | hist) . . (+11) . . Design with System Verilog and Verilog 2001 files (current)
- 11:47, 12 February 2019 (diff | hist) . . (+19) . . m Main Page
- 17:41, 28 December 2018 (diff | hist) . . (+1,087) . . Top level module with interface ports (current)
- 17:27, 28 December 2018 (diff | hist) . . (+1,706) . . N Defined macros become undefined - MFCU vs SFCU (Created page with "'''Q: I have macros defined in a separate input file. Why does Verific analyzer complain about "undefined macros" in SystemVerilog mode but not in Verilog 2K mode?''' SystemV...")
- 17:13, 28 December 2018 (diff | hist) . . (+1) . . Main Page
- 17:12, 28 December 2018 (diff | hist) . . (+157) . . Main Page
- 17:04, 28 December 2018 (diff | hist) . . (+24) . . Main Page
- 16:19, 28 December 2018 (diff | hist) . . (+851) . . N Top level module with interface ports (Created page with "'''Q: How to elaborate top-level module with interface ports.''' When I elaborate a top-level module with interface ports, Verific issues a warning message and stops the elab...")
- 14:07, 28 December 2018 (diff | hist) . . (+120) . . Main Page
- 10:30, 26 November 2018 (diff | hist) . . (-773) . . Talk:Main Page (Blanked the page) (current)
- 12:26, 11 September 2018 (diff | hist) . . (+119) . . Does Verific support XMR?
- 11:58, 31 August 2018 (diff | hist) . . (+54) . . Support IEEE 1735 encryption standard (current)
- 18:03, 30 August 2018 (diff | hist) . . (+678) . . N Support IEEE 1735 encryption standard (Created page with "'''Q:Does Verific provide support for IEEE 1735 encryption standard?''' Verific does not implement the decryption/encryption algorithms. This task is appropriately reserved t...")
- 18:00, 30 August 2018 (diff | hist) . . (+111) . . Main Page
- 17:11, 24 August 2018 (diff | hist) . . (+20) . . How to get type/initial value of parameters
- 17:10, 24 August 2018 (diff | hist) . . (+3) . . How to ignore parameters/generics in elaboration
- 17:10, 24 August 2018 (diff | hist) . . (+11) . . How to create a Netlist database from scratch (not from RTL input) (current)
- 17:09, 24 August 2018 (diff | hist) . . (+20) . . How to ignore parameters/generics in elaboration
- 17:01, 24 August 2018 (diff | hist) . . (+3,381) . . N How to create a Netlist database from scratch (not from RTL input) (Created page with "A Perl example: <nowiki> #!/usr/bin/perl use strict; push (@INC,"../../../extra_tests/pm"); require "Verific.pm"; # The global Libset is already at the top of the netlist...")
- 17:00, 24 August 2018 (diff | hist) . . (+142) . . Main Page
- 16:58, 24 August 2018 (diff | hist) . . (+31) . . Main Page
- 16:39, 24 August 2018 (diff | hist) . . (+299) . . Message handling
- 15:37, 24 August 2018 (diff | hist) . . (+865) . . N How to check for errors in analysis/elaboration (Created page with "'''Q:Verific clears the error count at various steps during analysis/elaboration. Is there a way to tell if these processes have errors?''' Verific follows an "optimistic" ap...")
- 15:29, 24 August 2018 (diff | hist) . . (+141) . . Main Page
- 12:42, 24 August 2018 (diff | hist) . . (+526) . . Constant expression replacement
- 12:31, 24 August 2018 (diff | hist) . . (+1,527) . . N How to ignore parameters/generics in elaboration (Created page with "'''Q:Is there a way to tell the elaborator to ignore certain parameters/generics so that the unit/module is not uniquified?''' Specific parameters/generics of specific module...")
- 12:23, 24 August 2018 (diff | hist) . . (+190) . . Main Page
- 12:14, 3 July 2017 (diff | hist) . . (+631) . . N Release version (Created page with "'''Q: How do I tell the version of a Verific software release? ''' The APIs: Message::ReleaseString() Message::ReleaseDate() respectively return the release string (e.g...")
- 12:05, 3 July 2017 (diff | hist) . . (+82) . . Main Page
- 15:02, 26 June 2017 (diff | hist) . . (+992) . . N Tcl library path (Created page with "'''Q: When trying to build, I get the error message: "/usr/bin/ld: cannot find -ltcl". How do I correct that problem?''' First, verify that you have tcl and tcl dev installed...")
- 14:49, 26 June 2017 (diff | hist) . . (+97) . . Main Page
- 16:36, 14 June 2017 (diff | hist) . . (-15) . . How to get type/initial value of parameters
- 13:35, 14 June 2017 (diff | hist) . . (+19) . . Does Verific support XMR?
- 13:34, 14 June 2017 (diff | hist) . . (+1) . . Does Verific support XMR?
- 10:36, 14 June 2017 (diff | hist) . . (+561) . . N How to get enums from Verilog parsetree (Created page with "'''Q: From the parsetree, how can I get the enums declared in a module?''' You can use the following code snippet: VeriModule *mod = ... ; VeriScope *scope = mod->GetSco...") (current)
- 10:32, 14 June 2017 (diff | hist) . . (+123) . . Main Page
- 16:47, 11 May 2017 (diff | hist) . . (+696) . . N How to identify packages being imported into a module (Created page with "'''Q: How do I identify packages being imported into a module?''' Code example: MapIter mi ; VeriModule *mod ; FOREACH_VERILOG_MODULE(mi, mod) { if (!mod || !mod->...") (current)
- 16:46, 11 May 2017 (diff | hist) . . (0) . . Main Page
- 16:46, 11 May 2017 (diff | hist) . . (+129) . . m Main Page
- 15:22, 6 April 2017 (diff | hist) . . (+385) . . N Instance - Module binding order (Created page with "'''Q: Verilog has many ways to find modules not in the file being directly read: -L, -v, -y, .... There may be more than one module of the same name. What is the order of bind...")
- 15:16, 6 April 2017 (diff | hist) . . (+100) . . Main Page
- 14:42, 6 April 2017 (diff | hist) . . (+741) . . N How to find port dimensions (Created page with "'''Q: How do I get port dimensions?''' A port can have multiple (packed/unpacked) dimensions like "module test (input [1:0][2:3] in1 [4:5][6:7]);". Below is a code excerpt in...") (current)
- 14:39, 6 April 2017 (diff | hist) . . (+75) . . Main Page
- 16:33, 5 April 2017 (diff | hist) . . (+836) . . N How to get library containing nested module (Created page with "'''Q: How do I get the library that contains the module nested inside another module?''' Take the following example: 1 module top (output o, input i1, i2, i3); 2 logic...")
- 16:26, 5 April 2017 (diff | hist) . . (+141) . . Main Page
- 12:55, 5 April 2017 (diff | hist) . . (+3) . . What languages can I use with Verific software?
- 16:45, 22 March 2017 (diff | hist) . . (+1,896) . . N How to get linefile information of macro definitions (Created page with "'''Q: How do I get linefile information of macro definitions?''' Take the following example: 1 `define A 2 `define B 10 3 `define C(a) a 4 `define D(a, b) a + b 5...") (current)
- 16:31, 22 March 2017 (diff | hist) . . (+126) . . m Main Page
- 15:03, 16 March 2017 (diff | hist) . . (-85) . . Does Verific support XMR?
- 13:29, 10 February 2017 (diff | hist) . . (+1) . . How to change name of id in Verilog parsetree
- 13:29, 10 February 2017 (diff | hist) . . (+433) . . N How to change name of id in Verilog parsetree (Created page with "'''Q:How do I change the name of an id (VeriIdDef) in Verilog parsetree?''' Name of identifier can be changed using following steps: 1. Get the scope where identifier is dec...")
- 13:23, 10 February 2017 (diff | hist) . . (+131) . . m Main Page
- 13:20, 8 December 2016 (diff | hist) . . (+145) . . m Original RTL language (current)
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