Difference between revisions of "Main Page"
From Verific Design Automation FAQ
(107 intermediate revisions by 4 users not shown) | |||
Line 1: | Line 1: | ||
'''General''' | '''General''' | ||
* [[How to get best support from Verific | '''''How to get best support from Verific''''']] | * [[How to get best support from Verific | '''''How to get best support from Verific''''']] | ||
+ | * [[Source code customization & Stable release services | Source code customization & Stable release services]] | ||
+ | * [[How to save computer resources | How to save computer resources (memory consumption & runtime)]] | ||
* [[Original RTL language | How do I know what language a Netlist in the netlist database comes from?]] | * [[Original RTL language | How do I know what language a Netlist in the netlist database comes from?]] | ||
* [[Verific data structures | What are the data structures in Verific?]] | * [[Verific data structures | What are the data structures in Verific?]] | ||
Line 7: | Line 9: | ||
* [[Does Verific support XMR?| Does Verific support cross module references (XMR)?]] | * [[Does Verific support XMR?| Does Verific support cross module references (XMR)?]] | ||
* [[Compile-time/run-time flags | Are there options to control Verific software's behavior? Compile-time & run-time flags.]] | * [[Compile-time/run-time flags | Are there options to control Verific software's behavior? Compile-time & run-time flags.]] | ||
− | * [[Message handling | How do I downgrade/upgrade messages from Verific? ]] | + | * [[Message handling | How do I downgrade/upgrade messages from Verific? How do I get messages with more details?]] |
* [[Release version | How do I tell the version of a Verific software release? ]] | * [[Release version | How do I tell the version of a Verific software release? ]] | ||
+ | * [[Simulation models for Verific primitives | Where do I find simulation models for Verific primitives (VERIFIC_XOR, VERIFIC_DFFRS, ....)? ]] | ||
* [[Tcl library path| How to correct building (linking) issue "/usr/bin/ld: cannot find -ltcl"]] | * [[Tcl library path| How to correct building (linking) issue "/usr/bin/ld: cannot find -ltcl"]] | ||
+ | * [[LineFile data from input files | LineFile data from input files]] | ||
+ | * [[Difference between RTL and gate-level simulations - Flipflop with async set and async reset | Difference between RTL and gate-level simulations - Flipflop with async set and async reset]] | ||
+ | * [[Preserving user nets - preventing nets from being optimized away | Preserving user nets - preventing nets from being optimized away]] | ||
+ | * [[Python pretty-printer for gdb | Python pretty-printer for gdb]] | ||
'''Input: VHDL, Verilog (and SystemVerilog), Liberty, EDIF''' | '''Input: VHDL, Verilog (and SystemVerilog), Liberty, EDIF''' | ||
Line 15: | Line 22: | ||
* [[Included files associated with a Verilog source file | Verilog: How do I get the list of included files associated with a Verilog source file?]] | * [[Included files associated with a Verilog source file | Verilog: How do I get the list of included files associated with a Verilog source file?]] | ||
* [[How to get type/initial value of parameters | Verilog: How to get type/initial value of parameters.]] | * [[How to get type/initial value of parameters | Verilog: How to get type/initial value of parameters.]] | ||
− | * [[Verilog ports being renamed | Verilog: | + | * [[Verilog ports being renamed | Verilog: Port Expressions]] |
* [[Design with System Verilog and Verilog 2001 files | Verilog: For a design consisting of a mixture of Verilog 2001 and SystemVerilog input files, should I parse all the files as SystemVerilog?]] | * [[Design with System Verilog and Verilog 2001 files | Verilog: For a design consisting of a mixture of Verilog 2001 and SystemVerilog input files, should I parse all the files as SystemVerilog?]] | ||
* [[How to get module ports from Verilog parsetree | Verilog: From the Verilog parsetree, how can I get the ports of a module?]] | * [[How to get module ports from Verilog parsetree | Verilog: From the Verilog parsetree, how can I get the ports of a module?]] | ||
* [[How to change name of id in Verilog parsetree | Verilog: How do I change the name of an id (VeriidDef) in Verilog parsetree?]] | * [[How to change name of id in Verilog parsetree | Verilog: How do I change the name of an id (VeriidDef) in Verilog parsetree?]] | ||
− | * [[How to get library containing nested module | Verilog: How do I get the library that contains the | + | * [[How to get library containing nested module | Verilog: How do I get nested modules and get the library that contains the nested module?]] |
* [[How to get linefile information of macro definitions | Verilog: How do I get linefile information of macro definitions?]] | * [[How to get linefile information of macro definitions | Verilog: How do I get linefile information of macro definitions?]] | ||
* [[How to find port dimensions | Verilog: How do I get port dimensions?]] | * [[How to find port dimensions | Verilog: How do I get port dimensions?]] | ||
* [[Instance - Module binding order | Verilog: What is the order of binding modules to instances?]] | * [[Instance - Module binding order | Verilog: What is the order of binding modules to instances?]] | ||
+ | * [[How Verific elaborator handles blackboxes/unknown boxes | Verilog: How Verific elaborator handles blackboxes/unknown boxes]] | ||
* [[Constant expression replacement | Verilog: Does Verific replace constant expressions with their respective values?]] | * [[Constant expression replacement | Verilog: Does Verific replace constant expressions with their respective values?]] | ||
+ | * [[Modules with '_1' '_2' suffix in their names | Verilog: After static elaboration, there are modules with "_1", "_2", ..., suffix in their names. Why?]] | ||
* [[Defined macros become undefined - MFCU vs SFCU | SystemVerilog: Why does Verific complain about undefined macros for macros defined in a different file (Compilation Unit)?]] | * [[Defined macros become undefined - MFCU vs SFCU | SystemVerilog: Why does Verific complain about undefined macros for macros defined in a different file (Compilation Unit)?]] | ||
+ | * [[Notes on analysis | SystemVerilog: Notes on analysis]] | ||
* [[How to get enums from Verilog parsetree | SystemVerilog: From the parsetree, how can I get the enums declared in a module?]] | * [[How to get enums from Verilog parsetree | SystemVerilog: From the parsetree, how can I get the enums declared in a module?]] | ||
* [[How to identify packages being imported into a module | SystemVerilog: How do I identify packages being imported into a module?]] | * [[How to identify packages being imported into a module | SystemVerilog: How do I identify packages being imported into a module?]] | ||
Line 30: | Line 40: | ||
* [[Top level module with interface ports | SystemVerilog: Support for SystemVerilog top level module with interface ports.]] | * [[Top level module with interface ports | SystemVerilog: Support for SystemVerilog top level module with interface ports.]] | ||
* [[Design with VHDL-1993 and VHDL-2008 files | VHDL: VHDL-1993 and VHDL-2008 each has its own IEEE library set. How do I analyze/elaborate a design with a mixture of files of different VHDL dialects (1993 and 2008)?]] | * [[Design with VHDL-1993 and VHDL-2008 files | VHDL: VHDL-1993 and VHDL-2008 each has its own IEEE library set. How do I analyze/elaborate a design with a mixture of files of different VHDL dialects (1993 and 2008)?]] | ||
+ | * [[Escaped identifiers in RTL files and in Verific data structures | Verilog/VHDL: Escaped identifiers in RTL files and in Verific data structures]] | ||
* [[Prettyprint to a string | Verilog/VHDL: How to prettyprint a parsetree node to a string.]] | * [[Prettyprint to a string | Verilog/VHDL: How to prettyprint a parsetree node to a string.]] | ||
* [[Static elaboration | Verilog/VHDL: What does 'static elaboration' do?]] | * [[Static elaboration | Verilog/VHDL: What does 'static elaboration' do?]] | ||
+ | * [[How to ignore a (not used) parameter/generic in elaboration. | Verilog/VHDL: How to ignore a (not used) parameter/generic in elaboration.]] | ||
* [[What VeriModule* or VhdlPrimaryUnit* the Netlist comes from? | Verilog/VHDL: For a Netlist in the netlist database, is there a clean way to look back at what VeriModule* or VhdlPrimaryUnit* the Netlist was derived from?]] | * [[What VeriModule* or VhdlPrimaryUnit* the Netlist comes from? | Verilog/VHDL: For a Netlist in the netlist database, is there a clean way to look back at what VeriModule* or VhdlPrimaryUnit* the Netlist was derived from?]] | ||
* [[Cross-reference between the original RTL files and the elaborated netlist | Verilog/VHDL: Is there a way to cross-reference between the original RTL design files and the elaboration netlist?]] | * [[Cross-reference between the original RTL files and the elaborated netlist | Verilog/VHDL: Is there a way to cross-reference between the original RTL design files and the elaboration netlist?]] | ||
* [[How to ignore parameters/generics in elaboration | Verilog/VHDL: Is there a way to tell the elaborator to ignore certain parameters/generics so that the unit/module is not uniquified?]] | * [[How to ignore parameters/generics in elaboration | Verilog/VHDL: Is there a way to tell the elaborator to ignore certain parameters/generics so that the unit/module is not uniquified?]] | ||
* [[How to check for errors in analysis/elaboration | Verilog/VHDL: Is there a way to tell if the analysis/elaboration process has errors?]] | * [[How to check for errors in analysis/elaboration | Verilog/VHDL: Is there a way to tell if the analysis/elaboration process has errors?]] | ||
− | * [[Modules/design units with "_default" suffix in their names | Verilog/VHDL: After static elaboration, there are modules/design units with "_default" suffix in their names. Why? And what are they?]] | + | * [[Modules/design units with "_default" suffix in their names | Verilog/VHDL: After static elaboration, there are modules/design units/interfaces with "_default" suffix in their names. Why? And what are they?]] |
+ | * [[How to parse a string | Verilog/VHDL: How to parse a string - Example of adding a module to the parsetree]] | ||
* [[Support IEEE 1735 encryption standard | Verilog/VHDL: Does Verific support IEEE 1735 encryption standard?]] | * [[Support IEEE 1735 encryption standard | Verilog/VHDL: Does Verific support IEEE 1735 encryption standard?]] | ||
'''Netlist Database''' | '''Netlist Database''' | ||
+ | * [[Logic optimization across hierarchy boundaries | Netlist Database: Does Verific perform logic optimization across hierarchy boundaries?]] | ||
+ | * [[Bit-blasting a multi-port RAM instance | Netlist Database: Bit-blasting a multi-port RAM instance]] | ||
+ | * [[System attributes | Netlist Database: System attributes]] | ||
'''Output''' | '''Output''' | ||
Line 47: | Line 63: | ||
'''Code examples''' | '''Code examples''' | ||
− | * [[ | + | * [[How to use RegisterCallBackMsg() | Util/C++: How to use RegisterCallBackMsg()]] |
+ | * [[How to use MessageCallBackHandler Class | Util/C++: How to use MessageCallBackHandler Class]] | ||
+ | * [[How to use RegisterPragmaRefCallBack() | Util/C++: How to use RegisterPragmaRefCallBack()]] | ||
* [[Write out an encrypted netlist | Database/C++: Write out an encrypted netlist]] | * [[Write out an encrypted netlist | Database/C++: Write out an encrypted netlist]] | ||
* [[Extract clock enable | Database/C++: Extract clock enable]] | * [[Extract clock enable | Database/C++: Extract clock enable]] | ||
+ | * [[Black box, empty box, and unknown box | Database/C++: Black box, empty box, and unknown box]] | ||
+ | * [[Post processing port resolution of black boxes | Database/C++: Post processing port resolution of black boxes]] | ||
+ | * [[Finding hierarchical paths of a Netlist | Database/C++: Finding hierarchical paths of a Netlist]] | ||
+ | * [[Replacing Verific built-in primitives/operators with user implementations | Database/C++: Replacing Verific built-in primitives/operators with user implementations]] | ||
+ | * [[Hierarchy tree RTL elaboration | Database/Perl: Simple example of hierarchy tree elaboration]] | ||
+ | * [[Create a Netlist Database from scratch (not from RTL elaboration) | Database/Perl/TCL: Create a Netlist Database from scratch (not from RTL elaboration)]] | ||
+ | * [[Buffering signals and ungrouping | Database/Verilog: Buffering signals and ungrouping (flattening) in the Netlist Database]] | ||
+ | * [[Memory elements of a RamNet | Database/Verilog/C++: Memory elements of a RamNet]] | ||
* [[Process -f file and explore the Netlist Database (C++)| Database/Verilog/C++: Process -f file and explore the Netlist Database]] | * [[Process -f file and explore the Netlist Database (C++)| Database/Verilog/C++: Process -f file and explore the Netlist Database]] | ||
* [[Process -f file and explore the Netlist Database (py)| Database/Verilog/Python: Process -f file and explore the Netlist Database]] | * [[Process -f file and explore the Netlist Database (py)| Database/Verilog/Python: Process -f file and explore the Netlist Database]] | ||
+ | * [[Fanout cone and grouping | Database/Verilog/Perl: Fanout cone and grouping in the Netlist Database]] | ||
+ | * [[Simple example of visitor pattern | Verilog/C++: Simple examples of visitor pattern]] | ||
* [[Statically elaborate with different values of parameters | Verilog/C++: Statically elaborate with different values of parameters]] | * [[Statically elaborate with different values of parameters | Verilog/C++: Statically elaborate with different values of parameters]] | ||
− | * [[Type Range example | Verilog/C++: Type Range | + | * [[Prettyprint all modules in the design hierarchy | Verilog/C++: Prettyprint all modules in the design hierarchy]] |
− | * [[ | + | * [[Getting instances' parameters | Verilog/C++: Getting instances' parameters]] |
− | * [[ | + | * [[Accessing and evaluating module's parameters | Verilog/C++: Accessing and evaluating module's parameters]] |
− | *[[Access attributes of ports in parsetree | Verilog/Perl: Access attributes of ports in parsetree]] | + | * [[Visiting Hierarchical References (VeriSelectedName) | Verilog/C++: Visiting Hierarchical References (VeriSelectedName)]] |
+ | * [[Type Range example | Verilog/C++: Type Range example (simple)]] | ||
+ | * [[Using stream input to ignore input file | Verilog/C++: Using stream input to ignore input file]] | ||
+ | * [[How to ignore certain modules while analyzing input RTL files | Verilog/C++: How to ignore certain modules while analyzing input RTL files]] | ||
+ | * [[How to tell if a module has encrypted contents | Verilog/C++: How to tell if a module has encrypted contents]] | ||
+ | * [[Comment out a line using text based design modification and parsetree modification | Verilog/C++: Comment out a line using text-based design modification and parsetree modification]] | ||
+ | * [[Verilog/C++: How to use IsUserDeclared() : Example for port associations]] | ||
+ | * [[How to create new module in Verilog parsetree | Verilog/C++: How to create new module in Verilog parsetree]] | ||
+ | * [[In Verilog parsetree adding names to unnamed instances | Verilog/C++: In Verilog parsetree adding names to unnamed instances]] | ||
+ | * [[How to get full hierarchy ID path | Verilog/C++: How to get full hierarchy ID path]] | ||
+ | * [[How to traverse scope hierarchy | Verilog/C++: How to traverse scope hierarchy]] | ||
+ | * [[Access attributes in parsetree | Verilog/C++: How to access attributes in parsetree]] | ||
+ | * [[How to detect multiple-clock-edge condition in Verilog parsetree | Verilog/C++: How to detect multiple-clock-edge condition in Verilog parsetree]] | ||
+ | * [[How to get driving net of an instance | Verilog/C++: How to get driving net of an instance]] | ||
+ | * [[Parse select modules only and ignore the rest | Verilog/C++: Parse select modules only and ignore the rest]] | ||
+ | * [[Create DOT diagram of parse tree | Verilog/C++: Create DOT diagram of a parse tree]] | ||
+ | * [[Type Range example with multi-dimensional arrays| Verilog/C++/Perl: Type Range example with multi-dimensional arrays]] | ||
+ | * [[How to get linefile data of macros - Macro callback function | Verilog/C++/Perl/Python: How to get linefile data of macros - Macro callback function]] | ||
+ | * [[Where in RTL does it get assigned? | Verilog/C++/Perl/Python: Where in RTL does it get assigned?]] | ||
+ | * [[Access attributes of ports in parsetree | Verilog/Perl: Access attributes of ports in parsetree and from netlist]] | ||
+ | * [[Evaluate 'for-generate' loop | Verilog/C++: Evaluate 'for-generate' loop]] | ||
* [[Retrieve package name for user-defined variable types | SystemVerilog/C++/Python: Retrieve package name for user-defined variable types]] | * [[Retrieve package name for user-defined variable types | SystemVerilog/C++/Python: Retrieve package name for user-defined variable types]] | ||
* [[Pretty-print a module and the packages imported by the module | SystemVerilog/C++: Pretty-print a module and the packages imported by the module]] | * [[Pretty-print a module and the packages imported by the module | SystemVerilog/C++: Pretty-print a module and the packages imported by the module]] | ||
* [[How to get packed dimensions of enum | SystemVerilog/C++: How to get packed dimensions of enum]] | * [[How to get packed dimensions of enum | SystemVerilog/C++: How to get packed dimensions of enum]] | ||
− | * [[Traverse instances in parsetree | | + | * [[Simple examples of VHDL visitor pattern | VHDL/C++: Simple examples of VHDL visitor pattern]] |
+ | * [[Traverse instances in parsetree | VHDL/C++: Traverse instances in parsetree]] | ||
+ | * [[Parsing from data in memory | Verilog/VHDL/C++: Parsing from data in memory]] |
Revision as of 22:25, 27 February 2024
General
- How to get best support from Verific
- Source code customization & Stable release services
- How to save computer resources (memory consumption & runtime)
- How do I know what language a Netlist in the netlist database comes from?
- What are the data structures in Verific?
- How do I remove all Verific data structures in memory?
- Does Verific build control and data flow graph (CDFG)?
- Does Verific support cross module references (XMR)?
- Are there options to control Verific software's behavior? Compile-time & run-time flags.
- How do I downgrade/upgrade messages from Verific? How do I get messages with more details?
- How do I tell the version of a Verific software release?
- Where do I find simulation models for Verific primitives (VERIFIC_XOR, VERIFIC_DFFRS, ....)?
- How to correct building (linking) issue "/usr/bin/ld: cannot find -ltcl"
- LineFile data from input files
- Difference between RTL and gate-level simulations - Flipflop with async set and async reset
- Preserving user nets - preventing nets from being optimized away
- Python pretty-printer for gdb
Input: VHDL, Verilog (and SystemVerilog), Liberty, EDIF
- Verilog: I'm using -v, -y, .... After Verific is done with the analysis, how do I get a list of all the files being analyzed?
- Verilog: How do I get the list of included files associated with a Verilog source file?
- Verilog: How to get type/initial value of parameters.
- Verilog: Port Expressions
- Verilog: For a design consisting of a mixture of Verilog 2001 and SystemVerilog input files, should I parse all the files as SystemVerilog?
- Verilog: From the Verilog parsetree, how can I get the ports of a module?
- Verilog: How do I change the name of an id (VeriidDef) in Verilog parsetree?
- Verilog: How do I get nested modules and get the library that contains the nested module?
- Verilog: How do I get linefile information of macro definitions?
- Verilog: How do I get port dimensions?
- Verilog: What is the order of binding modules to instances?
- Verilog: How Verific elaborator handles blackboxes/unknown boxes
- Verilog: Does Verific replace constant expressions with their respective values?
- Verilog: After static elaboration, there are modules with "_1", "_2", ..., suffix in their names. Why?
- SystemVerilog: Why does Verific complain about undefined macros for macros defined in a different file (Compilation Unit)?
- SystemVerilog: Notes on analysis
- SystemVerilog: From the parsetree, how can I get the enums declared in a module?
- SystemVerilog: How do I identify packages being imported into a module?
- SystemVerilog: Support for SystemVerilog semaphore/process/mailbox constructs.
- SystemVerilog: Support for SystemVerilog top level module with interface ports.
- VHDL: VHDL-1993 and VHDL-2008 each has its own IEEE library set. How do I analyze/elaborate a design with a mixture of files of different VHDL dialects (1993 and 2008)?
- Verilog/VHDL: Escaped identifiers in RTL files and in Verific data structures
- Verilog/VHDL: How to prettyprint a parsetree node to a string.
- Verilog/VHDL: What does 'static elaboration' do?
- Verilog/VHDL: How to ignore a (not used) parameter/generic in elaboration.
- Verilog/VHDL: For a Netlist in the netlist database, is there a clean way to look back at what VeriModule* or VhdlPrimaryUnit* the Netlist was derived from?
- Verilog/VHDL: Is there a way to cross-reference between the original RTL design files and the elaboration netlist?
- Verilog/VHDL: Is there a way to tell the elaborator to ignore certain parameters/generics so that the unit/module is not uniquified?
- Verilog/VHDL: Is there a way to tell if the analysis/elaboration process has errors?
- Verilog/VHDL: After static elaboration, there are modules/design units/interfaces with "_default" suffix in their names. Why? And what are they?
- Verilog/VHDL: How to parse a string - Example of adding a module to the parsetree
- Verilog/VHDL: Does Verific support IEEE 1735 encryption standard?
Netlist Database
- Netlist Database: Does Verific perform logic optimization across hierarchy boundaries?
- Netlist Database: Bit-blasting a multi-port RAM instance
- Netlist Database: System attributes
Output
Scripting languages: TCL, Perl, Python
Code examples
- Util/C++: How to use RegisterCallBackMsg()
- Util/C++: How to use MessageCallBackHandler Class
- Util/C++: How to use RegisterPragmaRefCallBack()
- Database/C++: Write out an encrypted netlist
- Database/C++: Extract clock enable
- Database/C++: Black box, empty box, and unknown box
- Database/C++: Post processing port resolution of black boxes
- Database/C++: Finding hierarchical paths of a Netlist
- Database/C++: Replacing Verific built-in primitives/operators with user implementations
- Database/Perl: Simple example of hierarchy tree elaboration
- Database/Perl/TCL: Create a Netlist Database from scratch (not from RTL elaboration)
- Database/Verilog: Buffering signals and ungrouping (flattening) in the Netlist Database
- Database/Verilog/C++: Memory elements of a RamNet
- Database/Verilog/C++: Process -f file and explore the Netlist Database
- Database/Verilog/Python: Process -f file and explore the Netlist Database
- Database/Verilog/Perl: Fanout cone and grouping in the Netlist Database
- Verilog/C++: Simple examples of visitor pattern
- Verilog/C++: Statically elaborate with different values of parameters
- Verilog/C++: Prettyprint all modules in the design hierarchy
- Verilog/C++: Getting instances' parameters
- Verilog/C++: Accessing and evaluating module's parameters
- Verilog/C++: Visiting Hierarchical References (VeriSelectedName)
- Verilog/C++: Type Range example (simple)
- Verilog/C++: Using stream input to ignore input file
- Verilog/C++: How to ignore certain modules while analyzing input RTL files
- Verilog/C++: How to tell if a module has encrypted contents
- Verilog/C++: Comment out a line using text-based design modification and parsetree modification
- Verilog/C++: How to use IsUserDeclared() : Example for port associations
- Verilog/C++: How to create new module in Verilog parsetree
- Verilog/C++: In Verilog parsetree adding names to unnamed instances
- Verilog/C++: How to get full hierarchy ID path
- Verilog/C++: How to traverse scope hierarchy
- Verilog/C++: How to access attributes in parsetree
- Verilog/C++: How to detect multiple-clock-edge condition in Verilog parsetree
- Verilog/C++: How to get driving net of an instance
- Verilog/C++: Parse select modules only and ignore the rest
- Verilog/C++: Create DOT diagram of a parse tree
- Verilog/C++/Perl: Type Range example with multi-dimensional arrays
- Verilog/C++/Perl/Python: How to get linefile data of macros - Macro callback function
- Verilog/C++/Perl/Python: Where in RTL does it get assigned?
- Verilog/Perl: Access attributes of ports in parsetree and from netlist
- Verilog/C++: Evaluate 'for-generate' loop
- SystemVerilog/C++/Python: Retrieve package name for user-defined variable types
- SystemVerilog/C++: Pretty-print a module and the packages imported by the module
- SystemVerilog/C++: How to get packed dimensions of enum
- VHDL/C++: Simple examples of VHDL visitor pattern
- VHDL/C++: Traverse instances in parsetree
- Verilog/VHDL/C++: Parsing from data in memory